S/W

Application

Program

Upstream

Decrypt

CPU

and

North

Bridge

and

Graphics

Controller

TFP510

DVI-HDCP TX

(PC’s DVI Output)

PROM

Key

Decrypt

C Keys and KSV

Upstream

Encrypt

DE

Pixel Data

Clock

Input

Stream

Encrypted Keys

A Keys and KSV

D Keys and KSV

TFP501

DVI-HDCP RX

(Display’s DVI Input)

PROM

Key

Decrypt

Slave I/F

Channel 2

Channel 0

Channel C

HDCP Encrypted

TMDS Link

Encrypted Keys

B Keys and KSV

Channel 1

EDID

PROM

Control and Authentication and Key Exchange

KSV = Key Selection Vector

DE

Pixel Data

Clock

Output

Stream

TFP501

SLDS127C

– JULY 2001 – REVISED JULY 2011

www.ti.com

Figure 13. TI

's HDCP Implementation for PC and Display System

TFP501 CLOCKING AND DATA SYNCHRONIZATION

The TFP501 receives a clock reference from the DVI transmitter, such as the TFP510, that has a period equal to

data on Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate.

For example, the required pixel rate to support an UXGA resolution with 60 Hz refresh rate is 165 MHz. The

TMDS serial bit rate is 10x the pixel rate or 1.65 Gb/s. Due to the transmission of this high speed digital bit

stream on three separate channels (or twisted-pair wires) of long distances (3

–5 meters), phase synchronization

between the data steams and the input reference clock is not assured. In addition, skew between the three data

channels is common. The TFP501 uses a 4x oversampling scheme of the input data streams to achieve reliable

lines due to reflections and external noise sources is also typical of high-speed serial data transmission. The

TFP501 is designed for high jitter tolerance.

The input clock to the TFP501 is conditioned by a PLL (phase-locked-loop) to remove high frequency jitter from

the clock. The PLL provides four 10x clock outputs of different phases to locate and sync the TMDS data

streams (4x oversampling). During the active display interval, the pixel data is encoded to be transition

minimized; whereas, during the blanking interval, the control data is encoded to be transition maximized. A

DVI-compliant transmitter is required to transmit during the blanking interval for a minimum period of time,

Performing synchronization during the blanking interval, when the data is transition maximized, assures reliable

data bit boundary detection. Phase synchronization to the data streams is unique for each of the three input

channels and is maintained as long as the link remains active.

12

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© 2001–2011, Texas Instruments Incorporated