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TFP501PZP датащи(PDF) 5 Page - Texas Instruments |
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TFP501PZP датащи(HTML) 5 Page - Texas Instruments |
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5 / 24 page ![]() TFP501 www.ti.com SLDS127C – JULY 2001 – REVISED JULY 2011 PIN FUNCTIONS (continued) PIN I/O DESCRIPTION NAME NO. Rx2 – 81 I Channel-2 negative receiver input – Negative side of channel-2 TMDS low voltage signal differential input pair. Channel-1 positive receiver input – Positive side of channel-1 TMDS low voltage signal differential input pair. Rx1+ 83 I Channel-1 receives green pixel data in active display and CTL1 control signals in blanking. Rx1- 84 I Channel-1 negative receiver input – Negative side of channel-1 TMDS low voltage signal differential input pair. Channel-0 positive receiver input – Positive side of channel-0. TMDS low voltage signal differential input pair. Rx0+ 86 I Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blanking. Rx0- 87 I Channel-0 negative receiver input – Negative side of channel-0. TMDS low voltage signal differential input pair. RxC+ 89 I Clock positive receiver input – Positive side of reference clock. TMDS low voltage signal differential input pair. RxC- 90 I Clock negative receiver input – Negative side of reference clock. TMDS low voltage signal differential input pair. Sync detect – Output to signal when the link is active or inactive. The link is considered to be active when DE is actively switching. The TFP501 monitors the state DE to determine link activity. SCDT can be tied externally to PDO SCDT 8 O to power down the output drivers when the link is inactive. High: Active link Low: Inactive link Output drive strength select – Selects output drive strength for high or low current drive. (See dc specifications for IOH and IOL vs ST state). ST 3 I High : High drive strength Low : Low drive strength Staggered pixel select – An active low signal used in the 2-pixel/clock pixel mode (PIXS = high). Time staggers the even and odd pixel outputs to reduce ground bounce. Normal operation outputs the odd and even pixels simultaneously. STAG 7 I High : Normal simultaneous even/odd pixel output Low: Time staggered even/odd pixel output VSYNC 47 O Vertical sync output ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT DVDD, AVDD, Supply voltage range -0.3 4 V OVDD, PVDD Input voltage range, logic/analog signals -0.3 4 V Operating ambient temperature range 0 70 °C Tstg Storage temperature range –65 150 °C Tc Case temperature for 10 seconds 260 °C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C ESD protection, all pins Human Body Model 25 kV JEDEC latchup (EIA/JESD78) 100 mA (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT VDD (DVDD, AVDD, Supply voltage 3 3.3 3.6 V PVDD, OVDD) t(pixel) (1) Pixel time 6.06 40 ns RT Single ended analog input termination resistance (2) 45 50 57 Ω TA Operating free-air temperature 0 25 70 °C (1) tpix is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to t(pixel) when in 1-pixel/clock mode and 2 t(pixel) when in 2-pixel/clock mode. (2) The TFP501 is internally optimized using a laser trim process to precisely fix the single-ended termination impedance, RT to 50 Ω ±10%. Copyright © 2001–2011, Texas Instruments Incorporated 5 |
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