TFP501

SLDS127C

– JULY 2001 – REVISED JULY 2011

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PIN FUNCTIONS (continued)

PIN

I/O

DESCRIPTION

NAME

NO.

6, 38

HSYNC

48

O

Horizontal sync output

ODCK Polarity - Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals (HSYNC,

VSYNC, DE, CTL1-2 ) are latched.

Normal Mode:

OCK_INV

100

I

High : Latches output data on rising ODCK edge

Low : Latches output data on falling ODCK edge

Output data clock

– Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with DE,

ODCK

44

O

HSYNC, VSYNC and CTL[2:1] are synchronized to this clock.

19, 28 ,45,

OGND

Output driver ground

– Ground reference and current return for digital output drivers

58, 76

18, 29, 43,

Output driver VDD

– Power supply for output drivers. Nominally 3.3 V

57, 78

Power down

– An active low signal that controls the TFP501 power-down state. During power down all output buffers

are switched to a high-impedance state and brought low through a weak pulldown. All analog circuits are powered

down and all inputs are disabled, except for PD.

PD

2

I

If PD is left unconnected an internal pullup defaults the TFP501 to normal operation.

High : Normal operation

Low: Power down

Output drive power down

– An active low signal that controls the power-down state of the output drivers. During

output drive power down, the output drivers (except SCDT and CTL1) are driven to a high-impedance state. A weak

pulldown slowly pulls these outputs to a low level. When PDO is left unconnected an internal pullup defaults the

PDO

9

I

TFP501 to normal operation.

High : Normal operation/output drivers on

Low: Output drive power down.

PGND

98

PLL ground

– Ground reference and current return for internal PLL

Pixel select

– Selects between one or two pixel per clock output modes. During 2-pixel/clock mode, both even pixels,

QE[23:0], and odd pixels, QO[23:0], are output in tandem on a given clock cycle. During 1 pixel/clock, even and odd

pixels are output sequentially, one at a time, with the even pixel first, on the even pixel bus, QE[23:0]. (The first pixel

PIXS

4

I

per line is pixel-0, the even pixel. The second pixel per line is pixel-1, the odd pixel.)

High : 2-pixel/clock

Low: 1-pixel/clock

PROM_SCL

95

I/O

EEPROM_serial clock

PROM_SDA

96

I/O

EEPROM_serial data

97, 99

Even blue pixel output

– Output for even and odd green pixels when in 1-pixel/clock mode. Output for even only blue

pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.

QE[0:7]

10

–17

O

LSB: QE0/pin 10

MSB: QE7/pin 17

Even green pixel output

– Output for even and odd green pixels when in 1-pixel/clock mode. Output for even only

green pixel when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.

QE[8:15]

20

–27

O

LSB: QE8/pin 20

MSB: QE15/pin 27

Even red pixel output

– Output for even and odd red pixels when in 1-pixel/clock mode. Output for even only red pixel

when in 2-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.

QE[16:23]

30

–37

O

LSB: QE16/pin 30

MSB: QE23/pin 37

Odd blue pixel output

– Output for odd only blue pixel when in 2-pixel/clock mode. Not used, and held low, when in

1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.

QO[0:7]

49

–56

O

LSB: QO0/pin 49

MSB: QO7/pin 56

Odd green pixel output - Output for odd only green pixel when in 2-pixel/clock mode. Not used, and held low, when in

1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.

QO[8:15]

59

–66

O

LSB: QO8/pin 59

MSB: QO15/pin 66

Odd red pixel output - Output for odd only red pixel when in 2-pixel/clock mode. Not used, and held low, when in

1-pixel/clock mode. Output data is synchronized to the output data clock, ODCK.

QO[16:23]

69

–75, 77

O

LSB: QO16/pin 69

MSB: QO23/pin 77

RSVD

42

O

Reserved

– Must be tied high for normal operation.

Channel-2 positive receiver input

– Positive side of channel-2 TMDS low voltage signal differential input pair.

Rx2+

80

I

Channel-2 receives red pixel data in active display and CTL2 control signals in blanking.

4

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© 2001–2011, Texas Instruments Incorporated