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TFP501PZP датащи(PDF) 3 Page - Texas Instruments |
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TFP501PZP датащи(HTML) 3 Page - Texas Instruments |
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3 / 24 page ![]() _ + Latch Channel 2 _ + Latch Channel 1 _ + Latch Channel 0 _ + PLL T.M.D.S. Decoder CH2[9:0] CH1[9:0] CH0[9:0] RED[7:0] CTL2 GRN[7:0] CTL1 BLU[7:0] VSYNC HSYNC QE[23:0] QO[23:0] ODCK DE SCDT CTL2 CTL1 VSYNC HSYNC 1.8 V Regulator 3.3 V Internal 50 Ω Termination Rx2+ Rx2- Rx1+ Rx1- Rx0+ Rx0- RxC+ RxC- HDCP Decryption RED[7:0] CTL2 GRN[7:0] CTL1 BLU[7:0] VSYNC HSYNC Panel Interface I2C Master I/F for EEPROM PROM_SCL 3.3 V PROM_SDA Key Decryption RAM Block I2C Slave I/F for DDC DDC_SCL DDC_SA DDC_SDA I2C Control Registers TFP501 www.ti.com SLDS127C – JULY 2001 – REVISED JULY 2011 FUNCTIONAL BLOCK DIAGRAM PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. AGND 79 Analog Ground - Ground reference and current return for analog circuitry. AVDD 82, 85, 88, 91 Analog VDD – Power supply for analog circuitry. Nominally 3.3 V CAP 67 O Bypass capacito r – 4.7 µF tantalum and 0.01 µF ceramic capacitors connected to ground. General-purpose control signals – Used for user defined control. In normal mode CTL1 is not powered down via CTL[2:1] 41, 40 O PDO. Display data channel_serial address – I2C Slave address bit A0 for display data channel (DDC). Refer to I2C DDC_SA 94 I Interface section for more details. DDC_SCL 92 I/O Display data channel_serial clock – I2C Clock for the DDC. External pullup resistors = 10 kΩ and 3.3 V tolerant. DDC_SDA 93 I/O Display data channel_serial data – I2C Data for the DDC. External pullup resistors = 10 kΩ and 3.3 V tolerant. Output data enable – Used to indicate time of active video display versus nonactive display or blanking interval. During blanking, only HSYNC, VSYNC, and CTL1-2 are transmitted. During times of active display, or nonblanking, only pixel data, QE[23:0] and QO[23:0], is transmitted. DE 46 O High : active display interval Low: blanking interval Output clock data format – Controls the output clock (ODCK) format for either TFT or DSTN panel support. For TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high; otherwise, ODCK is held low when DE is low. DFO 1 I High : DSTN support/ODCK held low when DE = low Low: TFT support/ODCK runs continuously. DGND 5, 39, 68 Digital ground – Ground reference and current return for digital core Copyright © 2001–2011, Texas Instruments Incorporated 3 |
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