FIGURE 23. DP8459 Window Measurement Configuration

4.2 WINDOW TRUNCATION TESTING

The DP8459 static window truncation specification is an

aggregate figure within which the window margin loss

contributions from all relevant blocks in the data synchroniza-

tion chain are combined into the single parameter, t

The preliminary DP8459 static window specification, t

applies only to the factory-tested data rates of 10 Mb/s

(with RS0,1,2 = 010) and 20 Mb/s (with RS0,1,2 = 000), with

the component values as listed for each corresponding

data rate in

Figures 5, and 10, test configuration as shown

in

Figure 23, test procedure as shown in Figure 24, and

strobe word M = −2 for 10 Mbits/sec and M = −3 for 20

Mbits/sec. Significant variation in t

other filters and data rates is not expected.

The

test

algorithm

employed

in

the

outgoing

factory

measurement (screening) of t

DATA stream consisting of a long synchronization field with a

single, movable test bit at its end. This method is referred to as

static window testing, since the window in which the test bit is

inserted is fully stabilized and unable to react instantaneously

to the phase step introduced by the displaced bit. The standard

screening procedure employed for determining DP8459 static

window truncation is divided into two portions, one which

determines the location of the leading (front) window boundary

and one which determines the trailing (back) window

boundary. The DP8459 is made to cycle through the read

operation many times as a variable bit is moved, once per read

cycle, from outside the target window across the ideal leading

boundary and into the window. The bit is advanced toward the

center of the target window until it resides in a position where

it is able to be detected a large number of times consecutively,

guaranteeing VCO jitter immunity. The time displacement

between the bit’s valid detection position and the ideal leading

window boundary is recorded as t

negative if the actual window boundary resides outside the

ideal window.) The variable bit is then placed outside the

trailing window boundary and the variable bit is again moved,

once per read cycle, from outside the target window across the

ideal boundary and into the window. The bit continues to

advanced toward the center of the recognition region until it is

in a position where it is able to be read a large number of times

consecutively. The time displacement between the bit’s valid

detection position and the ideal trailing window boundary is

recorded as t

actual window boundary resides outside the ideal window due

to window encroachment.) The larger (more positive) of the

two (t

sequence is shown in

Figure 24. Tables of external component

values used for production screening of the DP8459 at various

data rates are shown in

Figures 5 and 10.

Window truncation evaluated within data patterns containing

shifted bits is a direct function of PLL dynamics which are

under Customer control, and thus is neither tested nor

specified.

TL/F/9322-24

Notes: SD and SCK outputs are buffered by Advanced Schottky gates to provide standardized, typical loading conditions.

CRC, CRD, CRE, RG, and ERD are driven by a pattern generator providing the appropriate sequences both to load the control register with the appropriate

strobe position information and to cycle the RG and ERD test routine as per

Figure 24 .

PrintDate=1996/07/31 PrintTime=11:06:10 ds009322 Rev. No. 1

Proof

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