DP8459 datasheet(20/35 Pages) NSC

номер детали	DP8459

подробное описание детали	All-Code Data Synchronizer

PDF	35 Pages

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производитель	NSC [National Semiconductor (TI)]

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e(t) = ∆θ[1−ωnt]exp(−ωnt) for ζ = 1;

e(t) = ∆θ {cosh(ζ

2−1)0.5

nt−

[

ζ/(ζ2−1)0.5]sinh(ζ2−1)0.5 ω

nt}exp(−ζωnt) for ζ>1.

(These equations are plotted in

Figure 19 and are supplied for

informational purposes only; an ideal zero phase start function

would not produce a phase step at lock initiation.)

FIGURE 18. Transient Phase-Error Versus the Dimensionless Parameter

nt Due to a Step in Frequency for Various

Loop Damping Factors,

ζ (from Ref. 4 by Permission of L. A. Hoffman)

FIGURE 19. Phase-Error Versus the Dimensionless Parameter

nt Due to a Step inPhase for Various Loop Damping

Factors,

ζ (from Ref. 4 by Permission of L. A. Hoffman)

Note that the phase error

e is measured with respect to the

divided (or gated) VCO phase, i.e., 2

π radians = N/(20 MHz) =

200 ns in this example.

Regarding requirement #2, the lock-in range (with no

cycle-slipping) can be shown to be equal to the open loop

transfer function multiplied by the loop ﬁlter impedance

evaluated at inﬁnite frequency

∆ω

L ≈ ±KBZf(s)|s→

∞

TL/F/9322-20

TL/F/9322-21

PrintDate=1996/07/31 PrintTime=11:06:04 ds009322 Rev. No. 1

Proof

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DP8459 датащи(PDF) 20 Page - National Semiconductor (TI)