Symbol

Parameter

Conditions

Min

Typ

Max

Units

t

PW-RFC

Width of REFERENCE CLOCK, High or

Low

8ns

t

PW-ERD

Width of ENCODED READ DATA

12 High

ns

18 Low

t

PW-CRE

Width of CONTROL REGISTER ENABLE,

40

ns

High or Low ( Note 2 )

t

SU-CRD

CONTROL REGISTER DATA Set-Up Time

20

ns

with Respect to CRC ( Note 2 )

t

H-CRD

CONTROL REGISTER DATA Hold Time

10

ns

with Respect to CRC ( Note 2 )

t

SU-CRE

CONTROL REGISTER ENABLE Set-Up

Time with Respect to CRC ( Note 2 )

20

ns

t

H-CRE

CONTROL REGISTER ENABLE Hold Time

20

ns

with Respect to CRC ( Note 2 )

t

PW-CRC

CONTROL REGISTER CLOCK Pulse

Width, Positive or Negative ( Note 2 )

40

ns

I

CPIN

Combined R

1000

µA

Note 1: PUMP UP and PUMP DOWN outputs have no current sinking capability and thus are excluded from this specification.

Note 2: Parameter guaranteed by correlation to characterization data. No outgoing test performed.

Note 3: Human body model; 120 picofarads through 1.5 k

Ω.

AC Electrical Characteristics

Over recommended V

Symbol

Parameter

Min

Typ

Max

Units

t

STOP

SYNC CLOCK Negative Transitions following READ

GATE until Data Lock ZPS Sequence Begins (VCO

Freezes)

23

—

t

RESTART

Positive ENCODED READ DATA Transitions following

2

—

VCO Freeze until VCO Restarts

t

READ ABORT

Number of REF CLOCK Cycles following READ GATE

Deactivation until REF CLOCK Lock ZPS Sequence

4

—

Begins

t

T

Window Truncation (Half Window Loss);

DP8459V-10

10 Mbit/sec (Note 1 )

3% x

τ

VCO

3.0

ns

DP8459V-25

20 Mbit/sec (Note 2 )

4% x

τ

VCO

2.5

ns

φ Linearity

Phase Range for Charge Pump Linearity

±

π

Radians

(wrt VCO)

K

VCO

VCO Gain Constant

1.0

ω

O

1.2

ω

O

1.6

ω

O

Rad/Sec V

f

MAX VCO

VCO Maximum Frequency; RS0 = RS1 = RS2 =

Logical ZERO

70

MHz

t

SD0

Time Skew between SYNC CLOCK Negative Edge

and SYNC DATA Negative Edge

010

ns

t

SD1

Time Skew between SYNC CLOCK Negative Edge

and SYNC DATA Positive Edge

010

ns

t

ZPSR

Zero Phase Start Trigger Bit Targeting Accuracy,

READ GATE Activation (READ) ( Note 4 )

2ns

t

PWPC

Width of PCT, PU or PD Outputs in Fully Stabilized

10

ns

Lock (ERD Free of Jitter); R-Pull-Down = 510

Ω

∆f

Automatic f

50

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15

PrintDate=1996/07/31 PrintTime=11:05:55 ds009322 Rev. No. 1

Proof

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