DP8459 datasheet(27/35 Pages) NSC

27 / 35 page

5.0 Multiple Data Rate Applications

The DP8459 may be rapidly and easily switched from one data

rate to another, conceivably from its highest to its lowest

speciﬁed data rate and vice versa, with a minimum of

adaptation effort. This capacity facilitates the employment of

the DP8459 for stepped data rate disk applications (constant

density recording, or CDR), or for the employment of a single

data synchronizer for multiple-media controllers as a cost and

space conserving measure, e.g., allowing a controller to

address tape, ﬂoppy disk and hard disk read channels on a

multiplexed basis while employing a single data separator.

DP8459 data rate changes require only the appropriate new

REFERENCE

CLOCK

frequency

applied

and

the

necessary new RANGE SELECT information be presented to

the chip in cases where the Customer chooses to employ

compromise loop and Timing Extractor ﬁlters. The Customer

may alternatively choose to employ a transmission gate

technique to multiplex between appropriate ﬁlter elements for

various operating data rates should the frequencies be

sufficiently different (e.g., streaming tape drive versus hard

disk drive).

6.0 PC Board Layout Recommendations

The DP8459 data synchronizer circuit has been designed to

minimize the sensitivities normally associated with phase

locked loops which operate within digital environments, and in

particular those within disk and tape memory systems. A list of

recommendations and precautions is made available here for

the Customer, however, such that the DP8459 environment

can be optimized and the best possible performance achieved

with the device.

1. A localized V

CC supply net or island should be established

for the device and all its associated passive components,

supplied by but separated from the main V

CC plane. The

local V

CC net should be tied to the main VCC plane at only

one point and bypassed to the ground plane at that point.

2. The DP8459 V

pins should be bypassed to ground

through the shortest electrical path possible between the

supply pins the ground pins themselves. Bypassing should

be achieved with a 0.1 µF ceramic capacitor in parallel with

a 1000 pF silver mica capacitor.

3. The main digital ground plane should be used for all

grounding associated with the device. Both Analog and

Digital ground pins should be tied to this plane.

4. All passive components associated with the DP8459

should be located as close to their respective device pins

as possible. Lead length should be minimized.

5. External passive components should be oriented so as to

minimize the length of the ground-return path between the

component’s ground plane tie point and the DP8459 Analog

ground pin.

6. In order to minimize pin parasitic capacitances, planing

(supply or ground) should not be placed between device pin

eyelets.

7. Digital signal lines should not be run adjacent to external

passive analog components associated with the device.

Digital signal lines should not be run between analog signal

pins or traces associated with the device.

8. Digital input noise experience by the device should be

minimized, i.e., it may be advisable to condition input

waveforms in order to reduce transient noise. This may be

done with a series damping resistor at the REFERENCE

CLOCK input (and perhaps at the ENCODED READ DATA

input) in high frequency systems. This would terminate

board

traces

and

thus

prevent

under-damped,

noise-producing switching transients at the device inputs.

9. Digital output loading should be minimized, i.e., if outputs

must drive large loads or long traces, employ buffering.

Pre-termination of PC traces driven by the SYNCHRO-

NIZED CLOCK and SYNC DATA outputs may be advisable

in high frequency systems (i.e., include series resistance

equivalent to the characteristic impedance of the PC board

trace).

10. All unused digital output pins should be allowed to ﬂoat,

unconnected to any trace.

11. The device should not be located in a region of the PC

board where large V

or ground plane currents are

Original Window Position

TL/F/9322-2

Early Strobe Window Position

TL/F/9322-3

Late Strobe Window Position

TL/F/9322-4

De-Skewed Window Position

TL/F/9322-5

http:\\www.national.com

PrintDate=1996/07/31 PrintTime=11:06:13 ds009322 Rev. No. 1

Proof

DP8459 датащи(PDF) 27 Page - National Semiconductor (TI)

DP8459 датащи(HTML) 27 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

датащи скачать

ссылки URL