DP8459 datasheet(18/35 Pages) NSC

18 / 35 page

Substituting,

The second order characteristic equation can be written as

follows:

2 +sK

BR1 +KB/C1 = s

2 +s2

ζω

n + ωn

Extracting the component values from these results,

Thus, one is able to select component values in accordance

with speciﬁc system requirements, i.e., with given VCO center

frequency (equivalent to REFERENCE CLOCK frequency), R

(in either high or low gain mode), N (the ratio of the VCO

frequency to the ENCODED READ DATA frequency), the

desired natural frequency of the loop, and the desired damping

ratio.

The natural frequency and the damping ratio may be extracted

from the component values to determine system behavior

under various conditions (differing data patterns, i.e., varying N

value; high gain or low gain; read or non-read mode):

n = [1.2 VCC fo/2RpNC1)]

0.5

Natural frequency Damping ratio

ζ = ω

n R1C1/2

3.1 2,7 CODE, 10 MBIT/SEC LOOP FILTERDESIGN

EXAMPLE

Initial Requirements and Deﬁnitions

This example illustrates a 10 MBit/sec 2,7 hard disk system

employing a 4T preamble ﬁeld (recorded at 1⁄4 the VCO

frequency, i.e., N = 4). The component derivations are not

meant to produce values which will be optimum for all systems

employing this data rate, code, and preamble type; this

exercise is for exemplary purposes only. (See National

Semiconductor Advanced Peripheral Processing Solutions

Mass Storage Handbook #1, 1986, AN-413, section 3.4, pages

1-43 through 1-48 for additional information regarding disk

system PLL ﬁlter design.)

Although the DP8459 provides a frequency acquisition feature

intended for use within the preamble, this design example will

be approached so as to achieve PLL dynamics which will avoid

the cycle-slipping phenomenon frequency-lock action is

normally employed to accommodate. Thus, the design will be

valid both for systems which do employ frequency lock as well

as for those which do not. Advantages gained by the use of

frequency-lock beyond that of extended lock-in range,

however, such as harmonic false lock avoidance and

quadrature lock avoidance, make the use of this feature

strongly advisable even with the intrinsic lock-in range

achieved by design in this example.

The DP8459 is conﬁgured here with the FREQ LOCK CON-

TROL input tied to the PREAMBLE DETECTED output, the

HIGH GAIN DISABLE input tied to the READ GATE input, and

the CHARGE PUMP OUTPUT tied to the VCO INPUT pin as

well as to the external loop ﬁlter components (see

Figure 17 ).

This establishes self-regulated frequency lock control, READ

GATE regulated Charge Pump gain, and single node loop

ﬁltering.

PrintDate=1996/07/31 PrintTime=11:06:01 ds009322 Rev. No. 1

Proof

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