DP8459 datasheet(14/35 Pages) NSC

14 / 35 page

start sequence in correct phase relationship with the

ENCODED READ DATA. Re-assertion (logical zero) of the

FREQUENCY LOCK CONTROL pin within a read operation

(following the normal FLC deassertion after lock is achieved) is

permissible; however, it should be noted that the initial phase

error of the Synchronization Field Matching Divider with

respect to the ENCODED READ DATA at FREQUENCY-

LOCK CONTROL re-assertion may be as large as M x

VCO

in magnitude, possibly resulting in an extended PLL settling

time.

ZERO PHASE START

The function of the zero phase start (ZPS) block is to clear the

Phase Comparator and freeze the VCO in a known phase

when a transition occurs at the READ GATE input (either high

or low), and restart the VCO in a precise, controlled phase with

respect to the newly selected input (ENCODED READ DATA

or REFERENCE CLOCK ÷ 2, respectively). The ZPS circuit

also resets the count state of the Synchronization ﬁeld

Matching Divider in anticipation of locking to speciﬁc preamble

information (when frequency lock is being employed), and

controls

the

operation

the

REFERENCE

CLOCK

multiplexer. ZPS operation at READ GATE assertion is aimed

at optimizing initial window alignment and thus minimizing

initial phase step and the resulting phase lock acquisition time.

ZPS is also employed at deassertion of READ GATE;

however, the ZPS phase alignment for the REFERENCE

CLOCK signal at READ GATE deassertion has been made

less stringent than for ENCODED READ DATA at READ GATE

assertion.

PREAMBLE PATTERN DETECTOR

The Preamble Pattern Detector block has a pattern-speciﬁc

recognition circuit keyed to search the ENCODED READ

DATA for the pattern selected at the SYNC PATTERN SELECT

inputs. The pattern search begins following the assertion of

READ GATE and the completion of the zero phase start

sequence, and continues until approximately 32 uninterrupted

ENCODED READ DATA pulses of the 1T, 2T or 3T pattern

have been detected, or until 16 uninterrupted ENCODED

READ DATA pulses of the 4T pattern have been detected (see

speciﬁcation tables). When this event occurs, the PREAMBLE

DETECTED output becomes active high (logical-one). The

output will then remain latched in the high state until READ

GATE is deasserted. The PREAMBLE DETECTED output may

be tied to the HIGH GAIN DISABLE input to regulate the gain

of the PLL during the preamble lock sequence, and/or tied to

the FREQUENCY LOCK CONTROL input for self-regulation

of frequency acquisition in hard or pseudo-hard sectored

systems.

±50% VCO FREQUENCY OFFSET DETECTOR

The Frequency Offset Detector is employed to constrain the

VCO frequency swing, preventing VCO runaway associated

with standard, wide-range voltage controlled oscillators. The

circuitry will sense the relative difference between the

REFERENCE CLOCK frequency and the VCO frequency,

sending a “charge-up” signal to the Charge Pump to correct

the VCO should a limit of approximately −50% in frequency

differential (VCO w.r.t. REF CLOCK) be exceeded, and

sending a “charge-down” signal to the Charge Pump to correct

the VCO should a limit of approximately +50% in frequency

differential be exceeded. The resulting voltage-clamping action

at the ﬁlter node(s) also prevents out-of-range control voltage

straying and thus speeds lock recovery.

SYNCHRONIZATION CLOCK OUTPUT MULTIPLEXER

This block issues the VCO signal following READ GATE

assertion and completion of the zero phase start sequence,

and issues the REFERENCE CLOCK input signal when the

READ GATE is deasserted. Multiplexer switching is achieved

without glitches. The output is intended to be used both for

read and write clock purposes. (Please note output loading

recommendations for this pin in Section 6.)

2.2 SPECIFICATION TABLES

Absolute Maximum Ratings

If Military/Aerospace speciﬁed devices are required,

please

contact

the

National

Semiconductor

Sales

Office/Distributors for availability and speciﬁcations.

Supply Voltage

TTL Inputs

Output Voltages

Input Current

NOM,RBOOST, CPO, VCOI, TEF)

2 mA

Storage Temperature

−65

˚C to +150˚C

Operating Temperature Range

˚Cto+70˚C

ESD Susceptibility ( Note 3 )

1500V

Operating Conditions

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Supply Voltage

4.75

5.00

5.25

Ambient Temperature

˚C

High Logic Level Output Current

SYNC CLOCK

−2000

µA

Others

−400

Low Logic Level Output Current

SYNC CLOCK

( Note 1 )

Others

High Logic Level Input Voltage

Low Logic Level Input Voltage

0.8

NRZ

Operating Data Rate Range

0.25

Mb/s

PrintDate=1996/07/31 PrintTime=11:05:54 ds009322 Rev. No. 1

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