DP8459 datasheet(6/35 Pages) NSC

6 / 35 page

allow for an increase in charge pump gain above the level set

by the R

NOMINAL pin. When the HIGH GAIN DISABLE pin

(HGD) is inactive (logical-zero), the R

BOOST

resistor is

electrically paralleled with the R

NOMINAL

for an elevated

charge pump gain. When HIGH GAIN DISABLE is active

(logical-one), only the R

NOMINAL resistor is employed to set the

pump current. The Charge Pump throughput gain is I

CPO = 2x

Rp where IRp = 0.25VCC/Rp,Rp = RNOM with HGD high, and

p = RNOM||RBOOST with HGD low. The Customer may choose

to conﬁgure the system for high gain prior to DP8459 preamble

detection by tying the HGD pin to the PDT output pin, or for

high gain only during REFERENCE CLOCK lock by tying the

HGD pin to the READ GATE pin. Other conﬁgurations may be

employed, if desired.

The DP8459 issues a clock waveform from the SYNCHRO-

NIZED CLOCK output which is derived from the REFERENCE

CLOCK input when the READ GATE is inactive (logical-zero),

and from the VCO signal following READ GATE assertion

(logical-one) and completion of the zero phase start sequence.

The

REFERENCE

CLOCK

signal

issued

from

the

SYNCHRONIZED CLOCK output during non-Read activity

and may be used as a write clock, if desired. Once data lock is

achieved and the SYNCHRONIZED CLOCK output is issuing

VCO, the SYNCHRONIZED DATA output and the SYNCHRO-

NIZED CLOCK output are held in a ﬁxed, speciﬁed timing

relationship for use by decoding/deserializing circuitry. The

SYNCHRONIZED CLOCK output multiplexer switching is

achieved without glitches, i.e., no pulse is narrower than 50%

of the VCO or REFERENCE CLOCK period.

The DP8459 provides a COAST control input which serves to

clear the phase comparator and disable charge pump action

whenever taken to an active, logical-zero level. This function is

made available to allow the PLL to be set to free-run,

undisturbed, while a detectable defect is being read from the

media in a region where re-initiation of the lock procedure is

impractical (e.g., data ﬁeld). External data controller circuitry is

responsible for the detection of the defect and issuance of the

COAST command. The primary application of this feature is

expected to be optical disk bright-spot avoidance, though it will

lend itself to other applications as well.

As in the previous family of National Semiconductor data

separators/synchronizers,

the

DP8459

provides

phase

comparator activity information to the Customer. The phase

comparator’s pump-up and pump-down outputs are brought

out to separate pins, PUMP UP (PU) and PUMP DOWN (PD).

The outputs are of the open-emitter type, requiring an external

“pull-down” resistor when in active use. These outputs serve to

indicate the relative displacement of the current data bit with

respect to the internal VCO phase (window center). When in

completely stabilized lock with no bit displacement, the

output(s) will issue a pulse of a ﬁnite, minimum-valued width

for each arriving data pulse. If any data pulse is displaced with

respect to the VCO phase, the corresponding output pulse will

widen by an amount equivalent to the bit displacement. These

output signals may be integrated over time and employed to

determine

the

average

magnitude

media

bit

shift.

Additionally, the pulse widening/narrowing effect bit displace-

ment has on the PU/PD outputs produces an amplitude

modulation of the output’s waveform. The waveform envelope,

when observed with a relatively slow oscilloscope time base,

can be employed for observation of PLL dynamics. This is

particularly useful if intrusive probing of the PLL ﬁlter nodes is

not desirable.

It is strongly recommended that the PU/PD outputs be left

“ﬂoating” (unconnected to any net or circuit element, including

the output pull-down resistor) in any application where they are

not

speciﬁcally

needed.

This

will

serve

minimize

unnecessary, spurious digital switching transients in the

vicinity of the DP8459, and thus improve noise performance.

The DP8459 provides a wide operating data rate range to

facilitate use within a broad base of applications, including

multiple data rate systems or constant density recording

(CDR). In order to achieve the speciﬁed 250 kbit /sec to 25

Mbit/sec span, the operation of the VCO has been divided into

6 contiguous frequency sub-ranges, with approximately a 2:1

ratio between adjacent range selections. Three inputs are

provided for selecting of the sub-ranges, RANGE SELECT 0, 1

and 2. Some code type restrictions have been placed on the

higher ranges of operating VCO frequency. See

Figure 3 for

the operating data rate truth table and allowed code type

versus VCO range selection.

The DP8459 allows for ﬂexible synchronization window strobe

control. The inputs CONTROL REGISTER DATA (CRD),

CONTROL REGISTER CLOCK (CRC), and CONTROL

ENABLE

(CRE)

are

conﬁgured

permit

interfacing

the

DP8459

the

MICROWIRE™

(or

equivalent) bus for entry of strobe information. Information is

serially shifted into the CONTROL REGISTER via the CRD

and CRC pins whenever the CRE pin is active (logical-zero).

When the CRE pin is inactive (logical-one), CRD and CRC are

ignored. The strobe function allows the Customer to shift the

synchronization window in 31 equal steps of magnitude t

S = M

x [1.8% x

VCO] from approximately 27% early to 27% late with

respect to nominal window position. This function may be

employed for margin testing (eg., approximately ±12%)or

error recovery read re-try operations (eg., approximately ±2%

to ±3%). Additionally, this feature allows the Customer to align

the center of the synchronization window to within one half

strobe step of ideal, regardless of the initial performance or

speciﬁcation of the DP8459. This window centering function

may be performed completely within the drive system itself

(auto-alignment) given the employment of an intelligent

window alignment routine. Such a routine would be conﬁgured

to determine the maximum error free early and late window

positions via the strobe function, and then would ﬁx the

DP8459 window in the arithmetic mean position (Section

4.3.3). See

Figure 4 for a window strobe truth table.

Note: In all DP8459 applications, provision must be made to load the

appropriate information into the Control Register.

PrintDate=1996/07/31 PrintTime=11:05:43 ds009322 Rev. No. 1

Proof

http:\\www.national.com

DP8459 датащи(PDF) 6 Page - National Semiconductor (TI)

DP8459 датащи(HTML) 6 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

датащи скачать

ссылки URL