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WM8993 датащи(PDF) 31 Page - Wolfson Microelectronics plc |
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WM8993 датащи(HTML) 31 Page - Wolfson Microelectronics plc |
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31 / 229 page ![]() Production Data WM8993 w PD, November 2010, Rev 4.0 31 TDM MODE In TDM mode, it is important that two ADC devices to not attempt to drive the ADCDAT pin simultaneously. The timing of the WM8993 ADCDAT tri-stating at the start and end of the data transmission is described below. Figure 5 Audio Interface Timing - TDM Mode Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER CONDITIONS MIN TYP MAX UNIT Audio Data Timing Information ADCDAT setup time from BCLK falling edge DCVDD =2.0V DBVDD = 3.6V 5 ns DCVDD = 1.08V DBVDD = 1.62V 15 ns ADCDAT release time from BCLK falling edge DCVDD = 2.0V DBVDD = 3.6V 5 ns DCVDD = 1.08V DBVDD = 1.62V 15 ns |
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