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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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WM8993 датащи(PDF) 30 Page - Wolfson Microelectronics plc |
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WM8993 датащи(HTML) 30 Page - Wolfson Microelectronics plc |
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30 / 229 page  WM8993 Production Data w PD, November 2010, Rev 4.0 30 SLAVE MODE Figure 4 Audio Interface Timing - Slave Mode Note that BCLK and LRCLK inputs can be inverted if required; Figure 4 shows the default, non- inverted polarity. Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Slave Mode BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns LRCLK set-up time to BCLK rising edge tLRSU 20 ns LRCLK hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns ADCDAT propagation delay from BCLK falling edge tDD 20 ns DACDAT set-up time to BCLK rising edge tDS 20 ns Note: BCLK period must always be greater than or equal to MCLK period. Note: the descriptions above assume non-inverted polarity of BCLK and LRCLK. |
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