WM8993 datasheet(87/229 Pages) WOLFSON

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Production Data

WM8993

PD, November 2010, Rev 4.0

DC SERVO ENABLE AND START-UP

The DC Servo circuit is enabled on HPOUT1L and HPOUT1R by setting DCS_ENA_CHAN_0 and

DCS_ENA_CHAN_1 respectively. When the DC Servo is enabled, the DC offset correction can be

commanded in a number of different ways, including single-shot and periodically recurring events.

Writing a logic 1 to DCS_TRIG_STARTUP_n initiates a series of DC offset measurements and

applies the necessary correction to the associated output; (‘n’ = 0 for Left channel, 1 for Right

channel). On completion, the headphone output will be within 1mV of AGND. This is the DC Servo

mode selected by the default Start-Up sequence. Completion of the DC offset correction triggered in

this way is indicated by the DCS_STARTUP_COMPLETE field, as described in Table 56. Typically,

this operation takes 86ms per channel.

For correct operation of the DC Servo Start-Up mode, it is important that there is no active audio

signal present on the signal path while the mode is running. The DC Servo Start-Up mode should be

scheduled at the correct position within the Headphone Output Enable sequence, as described in the

“Output Signal Path” section. All other stages of the analogue signal path should be fully enabled

prior to commanding the Start-Up mode; the DAC Digital Mute function should be used, where

appropriate, to ensure there is no active audio signal present during the DC Servo measurements.

Writing a logic 1 to DCS_TRIG_DAC_WR_n causes the DC offset correction to be set to the value

contained in the DCS_DAC_WR_VAL_n fields in Register R87. This mode is useful if the required

offset

correction

has

already

been

determined

and

stored;

faster

than

the

DCS_TRIG_STARTUP_n mode, but relies on the accuracy of the stored settings. Completion of the

DC offset correction triggered in this way is indicated by the DCS_DAC_WR_COMPLETE field, as

described in Table 56. Typically, this operation takes 2ms per channel.

For pop-free operation of the DC Servo DAC Write mode, it is important that the mode is scheduled

at the correct position within the Headphone Output Enable sequence, as described in the “Output

Signal Path” section.

When using either of the DC Servo options above, the status of the DC offset correction process is

indicated

the

DCS_CAL_COMPLETE

field;

this

the

logical

the

DCS_STARTUP_COMPLETE and DCS_DAC_WR_COMPLETE fields.

The DC Servo control fields associated with start-up operation are described in Table 56. It is

important to note that, to minimise audible pops/clicks, the Start-Up and DAC Write modes of DC

Servo operation should be commanded as part of a control sequence which includes muting and

shorting of the headphone outputs; a suitable sequence is defined in the default Start-Up sequence.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R84 (54h)

DC Servo 0

DCS_TRIG_START

UP_1

Writing 1 to this bit selects Start-

Up DC Servo mode for

HPOUT1R.

In readback, a value of 1

indicates that the DC Servo

Start-Up correction is in

progress.

DCS_TRIG_START

UP_0

Writing 1 to this bit selects Start-

Up DC Servo mode for

HPOUT1L.

In readback, a value of 1

indicates that the DC Servo

Start-Up correction is in

progress.

DCS_TRIG_DAC_W

R_1

Writing 1 to this bit selects DAC

Write DC Servo mode for

HPOUT1R.

In readback, a value of 1

indicates that the DC Servo DAC

Write correction is in progress.

DCS_TRIG_DAC_W

R_0

Writing 1 to this bit selects DAC

Write DC Servo mode for

HPOUT1L.

In readback, a value of 1

indicates that the DC Servo DAC

Write correction is in progress.

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