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WM8993 датащи(PDF) 29 Page - Wolfson Microelectronics plc |
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WM8993 датащи(HTML) 29 Page - Wolfson Microelectronics plc |
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29 / 229 page ![]() Production Data WM8993 w PD, November 2010, Rev 4.0 29 AUDIO INTERFACE TIMING MASTER MODE Figure 3 Audio Interface Timing - Master Mode Note that BCLK and LRCLK outputs can be inverted if required; Figure 3 shows the default, non- inverted polarity of these signals. Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode LRCLK propagation delay from BCLK falling edge tDL 20 ns ADCDAT propagation delay from BCLK falling edge tDDA 20 ns DACDAT setup time to BCLK rising edge tDST 20 ns DACDAT hold time from BCLK rising edge tDHT 10 ns Note that the descriptions above assume non-inverted polarity of BCLK and LRCLK. |
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