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BCM4354 датащи(PDF) 30 Page - Cypress Semiconductor |
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BCM4354 датащи(HTML) 30 Page - Cypress Semiconductor |
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30 / 192 page ![]() External Frequency Reference BCM4354 Data Sheet BROADCOM CONFIDENTIAL Broadcom® October 15, 2014 • 4354-DS109-R Page 29 Drive level External crystal must be able to tolerate this drive level. 200 – ––––µW Input impedance (WRF_XTAL_IN) Resistive – – – 30 100 – kΩ Capacitive –– 7.5 ––7.5 pF WRF_XTAL_IN Input low level DC-coupled digital signal –– –0–0.2 V WRF_XTAL_IN Input high level DC-coupled digital signal – – – 1.0 – 1.26 V WRF_XTAL_IN input voltage (see Figure 5) AC-coupled analog signal – – – 400 – 1200 mVp-p Duty cycle 37.4 MHz clock – – – 40 50 60 % Phase Noiseg (IEEE 802.11b/g) 37.4 MHz clock at 10 kHz offset – – – – – –129 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –136 dBc/Hz Phase Noiseg (IEEE 802.11a) 37.4 MHz clock at 10 kHz offset – – – – – –137 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –144 dBc/Hz Phase Noiseg (IEEE 802.11n, 2.4 GHz) 37.4 MHz clock at 10 kHz offset – – – – – –134 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –141 dBc/Hz Phase Noiseg,h (IEEE 802.11n, 5GHz) 37.4 MHz clock at 10 kHz offset – – – – – –142 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –149 dBc/Hz Phase Noiseg (IEEE 802.11ac, 5GHz) 37.4 MHz clock at 10 kHz offset – – – – – –150 dBc/Hz 37.4 MHz clock at 100 kHz offset – – – – – –157 dBc/Hz a. (Crystal) Use WRF_XTAL_IN and WRF_XTAL_OUT. b. See “External Frequency Reference” on page 28 for alternate connection methods. c. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high. Note that 52 MHz is not an auto–detected frequency using the LPO clock. e. The frequency step size is approximately 80 Hz resolution. f. It is the responsibility of the equipment designer to select oscillator components that comply with these specifications. g. Assumes that external clock has a flat phase noise response above 100 kHz. h. If the reference clock frequency is <35 MHz the phase noise requirements must be tightened by an additional 2dB. Table 3: Crystal Oscillator and External Clock —Requirements and Performance (Cont.) Parameter Conditions/Notes Crystala External Frequency Referenceb,c Min. Typ. Max. Min. Typ. Max. Units |
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