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BCM4354 датащи(PDF) 60 Page - Cypress Semiconductor |
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BCM4354 датащи(HTML) 60 Page - Cypress Semiconductor |
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60 / 192 page ![]() I2S Interface BCM4354 Data Sheet BROADCOM CONFIDENTIAL Broadcom® October 15, 2014 • 4354-DS109-R Page 59 I2S Timing Note: Timing values specified in Table 16 are relative to high and low threshold levels. Table 16: Timing for I2S Transmitters and Receivers Transmitter Receiver Notes Lower LImit Upper Limit Lower Limit Upper Limit Min. Max. Min. Max. Min. Max. Min. Max. Clock Period T Ttr –– – Tr ––– a a. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. Master Mode: Clock generated by transmitter or receiver HIGH tHC 0.35Ttr – – – 0.35Ttr ––– b b. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with respect to T. LOWtLC 0.35Ttr – – – 0.35Ttr ––– b Slave Mode: Clock accepted by transmitter or receiver HIGH tHC –0.35Ttr ––– 0.35Ttr –– c c. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. LOW tLC –0.35Ttr ––– 0.35Ttr –– c Rise time tRC – – 0.15Ttr ––––– d d. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr. Transmitter Delay tdtr –– – 0.8T –––– e e. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. Hold time thtr 0– –––––– d Receiver Setup time tsr –– ––– 0.2Tr –– f f. The data setup and hold time must not be less than the specified receiver setup and hold time. Hold time thr –– –––0–– f Note: The time periods specified in Figure 19 and Figure 20 are defined by the transmitter speed. The receiver specifications must match transmitter performance. |
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