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BCM4354 датащи(PDF) 48 Page - Cypress Semiconductor |
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BCM4354 датащи(HTML) 48 Page - Cypress Semiconductor |
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48 / 192 page ![]() PCM Interface BCM4354 Data Sheet BROADCOM CONFIDENTIAL Broadcom® October 15, 2014 • 4354-DS109-R Page 47 Burst PCM Mode In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host. PCM Interface Timing Short Frame Sync, Master Mode Figure 10: PCM Timing Diagram (Short Frame Sync, Master Mode) Table 7: PCM Interface Timing Specifications (Short Frame Sync, Master Mode) Ref No. Characteristics Minimum Typical Maximum Unit 1 PCM bit clock frequency – – 12 MHz 2 PCM bit clock LOW 41 – – ns 3 PCM bit clock HIGH 41 – – ns 4 PCM_SYNC delay 0 – 25 ns 5 PCM_OUT delay 0 – 25 ns 6 PCM_IN setup 8 – – ns 7 PCM_IN hold 8 – – ns 8 Delay from rising edge of PCM_BCLK during last bit period to PCM_OUT becoming high impedance 0 – 25 ns PCM _BCLK PCM _SYNC PCM _OUT 1 23 4 5 PCM _IN 6 8 HIGH IM PEDANCE 7 |
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