BCM4354 datasheet(74/192 Pages) CYPRESS

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PCI Express Interface

BCM4354 Data Sheet

BROADCOM CONFIDENTIAL

Broadcom®

October 15, 2014 • 4354-DS109-R

Page 73

Physical Layer

The physical layer of the PCIe provides a handshake mechanism between the data link layer and the high-speed

signaling used for Link data interchange. This layer is divided into the logical and electrical functional subblocks.

Both subblocks have dedicated transmit and receive units that allow for point-to-point communication between

the host and BCM4354 device. The transmit section prepares outgoing information passed from the data link

layer for transmission, and the receiver section identifies and prepares received information before passing it to

the data link layer. This process involves link initialization, configuration, scrambler, and data conversion into a

specific format.

Logical Subblock

The logical sub block primary functions are to prepare outgoing data from the data link layer for transmission

and identify received data before passing it to the data link layer.

Scrambler/Descrambler

This PCIe PHY component generates pseudo-random sequence for scrambling of data bytes and the idle

sequence. On the transmit side, scrambling is applied to characters prior to the 8b/10b encoding. On the receive

side, descrambling is applied to characters after 8b/10b decoding. Scrambling may be disabled in polling and

recovery for testing and debugging purposes.

8B/10B Encoder/Decoder

The PCIe core on the BCM4354 uses an 8b/10b encoder/decoder scheme to provide DC balancing,

synchronizing clock and data recovery, and error detection. The transmission code is specified in the ANSI

X3.230-1994, clause 11 and in IEEE 802.3z, 36.2.4.

Using this scheme, 8-bit data characters are treated as 3 bits and 5 bits mapped onto a 4-bit code group and a

6-bit code group, respectively. The control bit in conjunction with the data character is used to identify when to

encode one of the twelve Special Symbols included in the 8b/10b transmission code. These code groups are

concatenated to form a 10-bit symbol, which is then transmitted serially. Special Symbols are used for link

management, frame TLPs, and DLLPs, allowing these packets to be quickly identified and easily distinguished.

Elastic FIFO

An elastic FIFO is implemented in the receiver side to compensate for the differences between the transmit clock

domain and the receive clock domain, with worse case clock frequency specified at 600 ppm tolerance. As a

result, the transmit and receive clocks can shift one clock every 1666 clocks. In addition, the FIFO adaptively

adjusts the elastic level based on the relative frequency difference of the write and read clock. This technique

reduces the elastic FIFO size and the average receiver latency by half.

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