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BCM4354 датащи(PDF) 116 Page - Cypress Semiconductor

номер детали BCM4354
подробное описание детали  Single-Chip 5G Wi-Fi IEEE 802.11ac 2횞2 MAC/ Baseband/Radio with Integrated Bluetooth 4.1 and FM Receiver
PDF  192 Pages
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производитель  CYPRESS [Cypress Semiconductor]
домашняя страница  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

BCM4354 датащи(HTML) 116 Page - Cypress Semiconductor

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Signal Descriptions
BCM4354 Data Sheet
BROADCOM CONFIDENTIAL
Broadcom®
October 15, 2014 • 4354-DS109-R
Page 115
J5
BT_UART_TXD
O
UART serial output. Serial data output for the HCI
UART interface.
Bluetooth/FM I2S
J6
BT_I2S_CLK
I/O
I2S clock, can be master (output) or slave (input).
G6
BT_I2S_DO
I/O
I2S data output
G5
BT_I2S_DI
I/O
I2S data input
L6
BT_I2S_WS
I/O
I2S WS; can be master (output) or slave (input).
Bluetooth GPIO
–
BT_GPIO_2
I/O
Bluetooth general-purpose I/O
–
BT_GPIO_3
I/O
Bluetooth general-purpose I/O
K4
BT_GPIO_4
I/O
Bluetooth general-purpose I/O
–
BT_GPIO_5
I/O
Bluetooth general-purpose I/O
Miscellaneous
A10
WL_REG_ON
I
Used by PMU to power up or power down the internal
BCM4354 regulators used by the WLAN section.
Also, when deasserted, this pin holds the WLAN
section in reset. This pin has an internal 200 kΩ pull-
down resistor that is enabled by default. It can be
disabled through programming.
D10
BT_REG_ON
I
Used by PMU to power up or power down the internal
BCM4354 regulators used by the Bluetooth/FM
section. Also, when deasserted, this pin holds the
Bluetooth/FM section in reset. This pin has an internal
200 kΩ pull-down resistor that is enabled by default. It
can be disabled through programming.
L4
BT_DEV_WAKE
I/O
Bluetooth DEV_WAKE
J3
BT_HOST_WAKE
I/O
Bluetooth HOST_WAKE
Integrated Voltage Regulators
B11
SR_VDDBATA5V
I
Quiet VBAT
B12
SR_VDDBATP5V
I
Power VBAT
A11
SR_VLX
O
CBuck switching regulator output. Refer to Table 43
on page 158 for details of the inductor and capacitor
required on this output.
C12
LDO_VDD1P5
I
LNLDO input
E12
LDO_VDDBAT5V
I
LDO VBAT.
P11
WRF_XTAL_VDD1P5
I
XTAL LDO input (1.35V)
N10
WRF_XTAL_VDD1P2
O
XTAL LDO output (1.2V)
D11
VOUT_LNLDO
O
Output of LNLDO
C11
VOUT_CLDO
O
Output of core LDO
D12
VOUT_BTLDO2P5
O
Output of BT LDO
E11
VOUT_LDO3P3_B
O
Output of 3.3V LDO
Table 22: WLBGA Signal Descriptions
Ball#
Signal Name
Type Description



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