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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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P89C51RC2BA/01 датащи(PDF) 57 Page - NXP Semiconductors |
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P89C51RC2BA/01 датащи(HTML) 57 Page - NXP Semiconductors |
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57 / 68 page  Philips Semiconductors Preliminary data P89C51RA2/RB2/RC2/RD2xx 80C51 8-bit Flash microcontroller family 8KB/16KB/32KB/64KB ISP/IAP Flash with 512B/512B/512B/1KB RAM 2002 Jul 18 57 AC ELECTRICAL CHARACTERISTICS (12-CLOCK MODE) Tamb = 0 °C to +70 °C or –40 °C to +85 °C; VCC = 5 V ± 10%, VSS = 0 V1, 2, 3 VARIABLE CLOCK4 33 MHz CLOCK4 SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 42 Oscillator frequency 0 33 MHz tLHLL 42 ALE pulse width 2tCLCL–40 21 ns tAVLL 42 Address valid to ALE low tCLCL–25 5 ns tLLAX 42 Address hold after ALE low tCLCL–25 5 ns tLLIV 42 ALE low to valid instruction in 4tCLCL–65 55 ns tLLPL 42 ALE low to PSEN low tCLCL–25 5 ns tPLPH 42 PSEN pulse width 3tCLCL–45 45 ns tPLIV 42 PSEN low to valid instruction in 3tCLCL–60 30 ns tPXIX 42 Input instruction hold after PSEN 0 0 ns tPXIZ 42 Input instruction float after PSEN tCLCL–25 5 ns tAVIV 42 Address to valid instruction in 5tCLCL–80 70 ns tPLAZ 42 PSEN low to address float 10 10 ns Data Memory tRLRH 43, 44 RD pulse width 6tCLCL–100 82 ns tWLWH 43, 44 WR pulse width 6tCLCL–100 82 ns tRLDV 43, 44 RD low to valid data in 5tCLCL–90 60 ns tRHDX 43, 44 Data hold after RD 0 0 ns tRHDZ 43, 44 Data float after RD 2tCLCL–28 32 ns tLLDV 43, 44 ALE low to valid data in 8tCLCL–150 90 ns tAVDV 43, 44 Address to valid data in 9tCLCL–165 105 ns tLLWL 43, 44 ALE low to RD or WR low 3tCLCL–50 3tCLCL+50 40 140 ns tAVWL 43, 44 Address valid to WR low or RD low 4tCLCL–75 45 ns tQVWX 43, 44 Data valid to WR transition tCLCL–30 0 ns tWHQX 43, 44 Data hold after WR tCLCL–25 5 ns tQVWH 44 Data valid to WR high 7tCLCL–130 80 ns tRLAZ 43, 44 RD low to address float 0 0 ns tWHLH 43, 44 RD or WR high to ALE high tCLCL–25 tCLCL+25 5 55 ns External Clock tCHCX 46 High time 17 tCLCL–tCLCX ns tCLCX 46 Low time 17 tCLCL–tCHCX ns tCLCH 46 Rise time 5 ns tCHCL 46 Fall time 5 ns Shift Register tXLXL 45 Serial port clock cycle time 12tCLCL 360 ns tQVXH 45 Output data setup to clock rising edge 10tCLCL–133 167 ns tXHQX 45 Output data hold after clock rising edge 2tCLCL–80 50 ns tXHDX 45 Input data hold after clock rising edge 0 0 ns tXHDV 45 Clock rising edge to input data valid 10tCLCL–133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are tested to 3.5 MHz, but guaranteed to operate down to 0 Hz. |
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