AD7779 datasheet(7/97 Pages) AD

7 / 97 page

Data Sheet

AD7779

Rev. 0 | Page 7 of 97

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DC ACCURACY

INL

Endpoint method, PGAGAIN = 1

±7

±15

ppm of FSR

Other PGA gains

±3

±15

ppm of FSR

Offset Error

±40

±125

μV

Offset Error Drift

±0.5

μV/°C

vs. time

−2

μV/

1000 hrs

Offset Matching

μV

Gain Error

±0.1

% FS

Gain Drift vs. Temperature

PGAGAIN = 1

±45

ppm/°C

Gain Matching

±0.1

SAR ADC

Speed and Performance

Resolution

Bits

Analog Input Range

AVSS4 + 0.1

AVDD4 − 0.1

Analog Input Common-Mode

Range

AVSS4 + 0.1

(AVDD4 +

AVSS4)/2

AVDD4 − 0.1

Analog Input Leakage Current

±5

Throughput

256

kSPS

DC Accuracy

Differential mode

INL

1.5

LSB

DNL

No missing codes (12-bit)

−0.99

LSB

Offset

LSB

Gain

LSB

AC Performance

SNR

1 kHz

THD

1 kHz

−81

VCM PIN

Output

(AVDD1x +

AVSSx)/2

Load Current, IL

Load Regulation, ∆VOUT/∆IL

mV/mA

Short-Circuit Current

LOGIC INPUTS

Input High Voltage, VIH

0.7 × IOVDD

Input Low Voltage, VIL

0.4

Hysteresis

0.1

Input Currents

−10

+10

μA

LOGIC OUTPUTS3

Output High Voltage, VOH

IOVDD ≥ 3 V, ISOURCE = 1 mA

0.8 × IOVDD

2.3 ≤ IOVDD < 3 V, ISOURCE = 500 μA

0.8 × IOVDD

IOVDD < 2.3 V, ISOURCE = 200 μA

0.8 × IOVDD

Output Low Voltage, VOL

IOVDD ≥ 3 V, ISINK = 2 mA

0.4

2.3 ≤ IOVDD < 3 V, ISINK = 1 mA

0.4

IOVDD < 2.3 V, ISINK = 100 μA

0.4

Leakage Current

Floating state

−10

+10

μA

Output Capacitance

Floating state

Σ-Δ ADC Data Output Coding

Twos

complement

SAR ADC Data Output Coding

Binary

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