AD7779 datasheet(44/97 Pages) AD

44 / 97 page

AD7779

Data Sheet

Rev. 0 | Page 44 of 97

SPI SAR Diagnostic Mode (SPI Control Mode)

Setting Bit 5 in the GENERAL_USER_CONFIG_2 register

configures the SDO line to shift out data from the SAR ADC

conversions, as described in Table 26.

In SAR mode, the AD7779 internal registers can be written to,

but any readback command is ignored because the SDO data

frame is dedicated to shift out the conversion results from the

SAR ADC.

To exit this mode of operation, reset Bit 5 in the GENERAL_

USER_CONFIG_2 register.

The data on the SDO line during the SPI transfer contains a

4-bit 0010 header and 12 bits of the SAR conversion result if the

CRC is disabled.

When the CRC is enabled, a minimum frame length of 24 SCLKs

is required on SPI transfers. The 24 bits of data on the SDO line

consist of a 4-bit header (0010), 12 bits of data, and an 8-bit

CRC, as shown in Figure 103.

Per the SPI read/write register mode (see the SPI Read/Write

avoid unwanted writes to the internal register while the SAR

conversions are read back through the SDO line, it is recom-

mended to send a readback command, for example, 0x8000,

to the device, which is ignored because the SDO pin is used to

shift out the content of the SAR ADC.

If consecutives conversion are performed in the SAR ADC, read

back the result from the previous conversion before a new

conversion is generated. Otherwise, the results are corrupted.

-∆ Data, ADC Mode

In pin control mode, the SPI interface can be used to read back

the -Δ conversions as described in Table 17. In SPI control

mode, the SPI interface reads back the -Δ conversions by setting

GENERAL_USER_CONFIG_3, Bit 4, as described in Table 26; in

this mode, the AD7779 internal register can be written to, but any

readback command is ignored because the SDO data frame is

dedicated to shifting out the conversion results from the -Δ

ADCs. To avoid unwanted writes to the internal register, it is

recommended to send a readback command, for example, 0x8000,

to the device, which is ignored because the SDO pin is used to

shift out the content of the -Δ ADC.

The SDO pin data can be read back in any multiple of 8 bits, for

example, as 64 bits, 2 × 32 bits, 4 × 16 bits, or 8 × 8 bits.

SPI Software Reset

Keeping the SDI pin high during 64 consecutives clocks

generates a software reset.

R/W

A6A5A4

A2A1

D0 ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0

SDO

SCLK

SDI

010

SAR

ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0

Figure 103. SAR ADC/Diagnostic Mode—CRC Enabled

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