AD7779 datasheet(67/97 Pages) AD

67 / 97 page

Data Sheet

AD7779

Rev. 0 | Page 67 of 97

CHANNEL 6 SYNC OFFSET REGISTER

Address: 0x00F, Reset: 0x00, Name: CH6_SYNC_OFFSET

Channel Sync Offs et

[7:0] CH6_SYNC_OFFSET (R/W)

Table 59. Bit Descriptions for CH6_SYNC_OFFSET

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH6_SYNC_OFFSET

Channel Sync Offset

0x0

R/W

CHANNEL 7 SYNC OFFSET REGISTER

Address: 0x010, Reset: 0x00, Name: CH7_SYNC_OFFSET

Channel Sync Offs et

[7:0] CH7_SYNC_OFFSET (R/W)

Table 60. Bit Descriptions for CH7_SYNC_OFFSET

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

CH7_SYNC_OFFSET

Channel Sync Offset

0x0

R/W

GENERAL USER CONFIGURATION 1 REGISTER

Address: 0x011, Reset: 0x24, Name: GENERAL_USER_CONFIG_1

If all SD channels are disabled, s etting

this bit high allows DCLK to continue

toggling

Soft Reset

11: 1s t write.

10: 2nd write.

01: No Effect.

00: No Effect.

Power Mode

1: High Resolution.

0: Low Power (1/4)

PowerDown signal for internal os cillator.

Active Low

PowerDown VCM Buffer. Active Low

PowerDown SA. Active Low

PowerDown Internal Reference Output

Buffer. Active Low

[7] ALL_CH_DIS__MCLK_EN (R/W)

[1:0] SOFT_RESET (R/W)

[6] POWERMODE (R/W)

[2] PDB_RC_OSC (R/W)

[5] PDB_VCM (R/W)

[3] PDB_SAR (R/W)

[4] PDB_REFOUT_BUF (R/W)

Table 61. Bit Descriptions for GENERAL_USER_CONFIG_1

Bits

Bit Name

Settings

Description

Reset

Access

ALL_CH_DIS_MCLK_EN

If all Σ-Δ channels are disabled, setting this bit high allows DCLK to

continue toggling.

0x0

R/W

POWERMODE

Power Mode.

0x0

R/W

Low power (1/4).

High resolution.

PDB_VCM

Power Down VCM Buffer. Active low.

0x1

R/W

PDB_REFOUT_BUF

Power Down Internal Reference Output Buffer. Active low.

0x0

R/W

PDB_SAR

Power Down SAR. Active low.

0x0

R/W

PDB_RC_OSC

Power Down Signal for Internal Oscillator. Active low.

0x1

R/W

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