AD7779 datasheet(35/97 Pages) AD

35 / 97 page

Data Sheet

AD7779

Rev. 0 | Page 35 of 97

ADC

MODULATOR

SINC

FILTER

DATA

INTERFACE

CONTROL

MCLK DIVIDER

HIGH RESOLUTION MODE: MCLK/4

LOW POWER MODE: MCLK/8

DCLK DIVIDER

1, 2, 4, 8, 16, 32, 64, 128

DEC RATES = ×128, ×256, ×512, ×1024, ×2048, ×4095.99

MOD_MCLK

DCLKx

DRDY

DOUT3

DOUT0

PGA

AINx+

MCLK

AINx–

Figure 93. Clock Generation on the AD7779

The reference buffers can be operated in three different modes:

buffer enabled mode, buffer bypassed mode, and buffer

precharged mode.

In buffer enabled mode, the buffer is fully enabled, minimizing

the current requirements from the external references. Note that

the buffer output voltage headroom is ±100 mV from the rails.

In buffer bypassed mode, the external reference is directly

connected to the ADC reference capacitors; the reference must

provide enough current to correctly charge the internal ADC

reference capacitors. In this mode of operation, a degradation in

crosstalk is expected because the ADC channels are not isolated

from each other.

Buffer precharged (pre-Q) mode is the default operation mode.

It is a hybrid mode where the internal reference buffers are

connected during the initial acquisition time to precharge the

internal ADC reference capacitors. During the final phase of the

acquisition, the reference is connected directly to the ADC

capacitors. This mode has some benefits compared to the buffer

enabled and buffer bypassed modes. In buffer precharged

mode,



the reference current requirements are minimized

compared to buffer bypassed mode



the noise contribution from the internal reference buffers

is removed (compared to buffer enabled mode)

In buffer precharged mode, the headroom/footroom of the

buffer reference is not applicable because the reference sets the

final voltage in the ADC reference capacitors.

INTEGRATED LDOs

The AD7779 has three internal LDOs to regulate the internal

supplies: two LDOs for the analog block and one LDO for the

digital core. The internal LDOs requires an external 1 μF

decoupling capacitor on the DREGCAP, AREG1CAP, and

the AREG2CAP pins. The LDO slew rate may be low because

it depends on the main supply slew rate; therefore, a hardware

reset generated by pulsing the RESET pin at power-up is required

to guarantee that the digital block initializes correctly.

CLOCKING AND SAMPLING

The AD7779 includes eight -Δ ADC cores. Each ADC receives

the same master clock signal. The AD7779 requires a maximum

external MCLK frequency of 8192 kHz for high resolution mode

and 4096 kHz for low power mode. The MCLK is internally

divided by 4 in high performance mode and by 8 in low power

mode to produce the modulator MCLK (MOD_MCLK) signal

used as the modulator sampling clock for the ADCs. The MCLK

can be decreased to accommodate lower ODRs if the minimum

ODR selected by the SINC filter is not low enough. If the external

clock is lower than 250 kHz, set the CLK_QUAL_DIS bit (in

SPI control mode only).

The AD7779 integrates an internal oscillator clock that initializes

the internal registers at power-up. The CLK_SEL pin defines the

external clock used after initialization (see Table 16).

Table 16. Clock Sources

CLK_SEL State

Clock Source

Connection

CMOS

Input to XTAL2/MCLK, IOVDD

logic level. XTAL1 must be

tied to DGND.

Crystal

Connected between XTAL1

and XTAL2/MCLK.

The MCLK signal generates the DCLK output signal, which in

turn clocks the -Δ conversion data from the AD7779, as

shown in Figure 93.

DIGITAL RESET AND SYNCHRONIZATION PINS

An external pulse in the SYNC_IN pin generates the internal

reset of the digital block; this pulse does not affect the data

programmed in the internal registers. A pulse in this pin is

required in two cases as follows:



After updating one or more registers directly related to the

sinc3 filter. These are power mode, offset, gain, and phase

compensation.



To synchronize multiple devices.

AD7779 датащи(PDF) 35 Page - Analog Devices

AD7779 датащи(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

датащи скачать

ссылки URL