RF430CL331HIPWR datasheet(13/60 Pages) TI1

13 / 60 page

RF430CL331H

www.ti.com

SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015

5.5

Communication Protocol

The tag is programmed and controlled by writing data into and reading data from the address map shown

in Table 5-2 through the I2C serial interface.

Table 5-2. User Address Map

RANGE

ADDRESS

SIZE

DESCRIPTION

0xFFFE

2 B

Control register

0xFFFC

2 B

Status register

0xFFFA

2 B

Interrupt Enable

0xFFF8

2 B

Interrupt Flags

0xFFF6

2 B

CRC Result (16-bit CCITT)

0xFFF4

2 B

CRC Length

0xFFF2

2 B

CRC Start Address

0xFFF0

2 B

Communication Watchdog Control register

0xFFEE

2 B

Version

Registers

0xFFEC

2 B

NDEF File ID register

0xFFEA

2 B

Host Response register

0xFFE8

2 B

NDEF Block Length register

0xFFE6

2 B

NDEF File Offset register

0xFFE4

2 B

Buffer Start register

0xFFE2

2 B

Reserved

0xFFE0

2 B

Reserved

0xFFDE

2 B

SWTX register

0xFFDC

2 B

Reserved

0xFFDA

2 B

Custom SW1 and SW2 Response

0x4000 to 0xFFDF

Reserved

0x0BB8 to 0x3FFF

13KB

Reserved (for example, for future extension of NDEF Memory size)

Buffer

0x0000 to 0x0BB7

3000 B

Buffer Memory

NOTE

Crossing range boundaries causes writes to be ignored and reads to return undefined data.

5.6

2C Protocol

A command is always initiated by the master by addressing the device using the specified I2C device

address. The device address is a 7-bit I2C address. The upper 4 bits are hard-coded, and the lower 3 bits

are programmable by the input pins E0, E1, and E2 (see Table 5-3).

Table 5-3. I2C Device Address

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

MSB

LSB

To write data, the device is addressed using the specified I2C device address with R/W = 0, followed by

the upper 8 bits of the first address to be written and the lower 8 bits of that address. Next (without a

repeated START), the data to be written starting at the specified address is received. With each data byte

received, the address is automatically incremented by 1. The write access is terminated by the STOP

condition on the I2C bus.

Detailed Description

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