RF430CL331HIPWR datasheet(35/60 Pages) TI1

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RF430CL331H

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SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015

5.11 Registers

NOTE

All 16-bit registers are in little-endian format: the least significant byte with bits 7-0 is at the

lowest address (this address is always even). The most significant byte with bits 15-8 is at

the highest address (this address is always odd).

5.11.1 General Control Register

Table 5-10. General Control Register

ADDRESS

Automatic

0xFFFF

Reserved

ACK On

Write

ADDRESS

Standby

0xFFFE

Reserved

BIP-8

INTO Drive

INTO High

Enable INT

Enable RF

SW-Reset

Enable

Table 5-11. General Control Register Description

BIT

FIELD

TYPE

RESET

DESCRIPTION

15-9

Reserved

Reserved for future use. Write with 0.

Enabling this bit causes an automatic acknowledgment to be sent when an

Update Binary command is received. The buffer must be read out immediately

(possibly while a new Update Binary command is being received over RF).

Automatic ACK On Write

R/W

0b = Manual acknowledgment of Update Binary command

1b = Automatic acknowledgment of Update Binary command

Reserved

R/W

Enables a low-power standby mode. The standby mode is entered if the RF

interface is disabled, the communication watchdog is disabled, and no serial

communication is ongoing.

Standby Enable

R/W

0b = Standby mode disabled

1b = Standby mode enabled

Enables BIP-8 communication mode (bit interleaved parity).

If BIP-8 is enabled, a separate running tally is kept of the parity (that is, the

number of ones that occur) for every bit position in the bytes included in the

BIP-8 calculation. The corresponding bit position of the BIP-8 byte is set to 1 if

the parity is currently odd and is set to 0 if the parity is even – resulting in an

overall even parity for each bit position including the BIP-8 byte.

BIP-8

R/W

All communication when this bit is set must follow the conventions defined in

the BIP-8 communication mode sections in Section 5.6.2.

0b = BIP-8 communication mode disabled

1b = BIP-8 communication mode enabled

Configuration of the interrupt output pin INTO

0b = Pin is Hi-Z if there is no pending interrupt. Application provides an external

pullup resistor if bit 3 (INTO High) = 0. Application provides an external pull-

INTO Drive

R/W

down resistor if bit 3 (INTO High) = 1.

1b = Pin is actively driven high or low if there is no pending interrupt. It is driven

high if bit 3 (INTO High) = 0. It is driven low if bit 3 (INTO High) = 1.

Configuration of the interrupt output pin INTO

INTO High

R/W

0b = Interrupts are signaled with an active low

1b = Interrupts are signaled with an active high

Detailed Description

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