RF430CL331HIPWR datasheet(10/60 Pages) TI1

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SDA

SCL

1/fSCL

tHD,DAT

tSU,DAT

tHD,STA

tSU,STA

tHD,STA

tSU,STO

tSP

RF430CL331H

SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015

www.ti.com

4.9

Timing and Switching Characteristics

4.9.1

Reset Timing

Table 4-1. I2C Power-up Timing

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

MIN

MAX

UNIT

tReady

Time after power up or reset until device is ready to communicate using I2C(1)

(1)

The device is ready to communicate after tReady(MAX) at the latest.

4.9.2

Serial Communication Protocol Timing

Table 4-2. I2C Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 4-1)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

SCL clock frequency (with Master supporting clock stretching

according to I2C standard, or when the device is not being

3.3 V

400

addressed)

fSCL

kHz

Write

3.3 V

120

SCL clock frequency (device being addressed by Master not

supporting clock stretching)

Read

3.3 V

100

fSCL ≤ 100 kHz

tHD,STA

Hold time (repeated) START

3.3 V

µs

fSCL > 100 kHz

0.6

fSCL ≤ 100 kHz

4.7

tSU,STA

Setup time for a repeated START

3.3 V

µs

fSCL > 100 kHz

0.6

tHD,DAT

Data hold time

3.3 V

tSU,DAT

Data setup time

3.3 V

250

tSU,STO

Setup time for STOP

3.3 V

µs

tSP

Pulse duration of spikes suppressed by input filter

3.3 V

6.25

Figure 4-1. I2C Mode Timing

Specifications

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