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RF430CL331HIPWR датащи(PDF) 29 Page - Texas Instruments |
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RF430CL331HIPWR датащи(HTML) 29 Page - Texas Instruments |
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29 / 60 page ![]() Block Requested 1. PCD ± Read Binary Request Filling Block 2. Host ± Service Request Being Transmitted 3. PCD/Host ± Data Being Transmitted (prefetch interrupt): Filling Now 0 Sent 4. PCD/Host ± Next Request (only prefetch interrupt): Being Transmitted Have Need Buffer shifted internally: L N Request Parameters: buffer_start_index = L length_requested = N - L 0 Entire Buffer Space (not to scale) Filling Now Sent 5. PCD/Host ± Next Request (only prefetch interrupt): Sent Being Transmitted Filling 6. PCD ± Next Request (General Type 4 Request interrupt) 8. Next: Cycle repeats (to Step 3) (up to limit) 7. Host ± Service Request: Sending N (<255 bytes) RF430CL331H www.ti.com SLASE18A – SEPTEMBER 2015 – REVISED NOVEMBER 2015 5.9.3.1 NDEF Read Command With Prefetch Internal Buffer Handling Figure 5-12. Read Buffer Flow (Prefetch Feature) The key feature with Prefetch is that while the Read Binary is being transmitted, the next packet can be sent out by the host controller and be filling the internal RF430CL331H buffer. Each request is stored in the subsequent buffer memory until the buffer limit is reached. When the buffer limit is reached, the remaining unsent data is shifted to the beginning of the buffer and what data is needed for the next request is requested (see Step 6). This command is requested using the General Type 4 request interrupt (not with a prefetch interrupt) because it does not happen during the time when the RF430CL331H is sending data over RF. Read buffer flow procedure (see Figure 5-12): 1. PCD requests a block of data. 2. PICC received the requests, sets up the internal register and asserts the INTO interrupt. 3. Host services the interrupt by supplying the data. PICC transmits the data. After starting to transmit the data, PICC issues a Read Prefetch interrupt. The host supplies the extra data while the RF communication is ongoing. 4. When the next Read Binary request comes, because the data is already cached, only the Prefetch interrupt is asserted. 5. This time a Prefetch interrupt is asserted, but only a portion of the data can be written because the buffer space is running out. 6. Because there is not enough data to service the Read Binary requests, a General Type 4 interrupt is asserted. The partial data that has been written previously is shifted to the beginning of the buffer and the only the remaining missing data is requested in the interrupt. 7. The complete data is sent out. The cycle repeats (the Prefetch interrupt is issued again). If a prefetch interrupt is issued for a file, but there is no more data to send, this interrupt can be canceled by servicing it by setting the data length sent to 0. Also if data was sent by a prefetch but it was not needed by the RF430CL331H (due to a different request by the PCD) that data is discarded and the new request handling initiated. Copyright © 2015, Texas Instruments Incorporated Detailed Description 29 Submit Documentation Feedback Product Folder Links: RF430CL331H |
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