MEC1322 datasheet(191/456 Pages) MICROCHIP

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DS00001719D-page 191

MEC1322

14.11.12 SCRATCHPAD REGISTER

5DSR

This bit is the complement of the Data Set Ready (nDSR) input. If bit

4 of the MCR is set to logic ‘1’, this bit is equivalent to DTR in the

MCR.

R0h

RESET

4CTS

This bit is the complement of the Clear To Send (nCTS) input. If bit 4

of the MCR is set to logic ‘1’, this bit is equivalent to nRTS in the

MCR.

R0h

RESET

3 DCD

Delta Data Carrier Detect (DDCD). Bit 3 indicates that the nDCD

input to the chip has changed state.

NOTE: Whenever bit 0, 1, 2, or 3 is set to a logic ‘1’, a MODEM Sta-

tus Interrupt is generated.

R0h

RESET

2RI

Trailing Edge of Ring Indicator (TERI). Bit 2 indicates that the nRI

input has changed from logic ‘0’ to logic ‘1’.

R0h

RESET

1DSR

Delta Data Set Ready (DDSR). Bit 1 indicates that the nDSR input

has changed state since the last time the MSR was read.

R0h

RESET

0CTS

Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to

the chip has changed state since the last time the MSR was read.

R0h

RESET

Note:

The Modem Status Register (MSR) only provides the current state of the UART MODEM control lines in

Loopback Mode. The MEC1322 does not support external connections for the MODEM Control inputs

(nCTS, nDSR, nRI and nDCD) or for the four MODEM Control outputs (nDTR, nRTS, OUT1 and OUT2).

Offset

07h

Bits

Description

Type

Default

Reset

Event

7:0 SCRATCH

This 8 bit read/write register has no effect on the operation of the

Serial Port. It is intended as a scratchpad register to be used by the

programmer to hold data temporarily.

R/W

RESET

Offset

06h

Bits

Description

Type

Default

Reset

Event

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