MEC1322 datasheet(189/456 Pages) MICROCHIP

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DS00001719D-page 189

MEC1322

14.11.10 LINE STATUS REGISTER

0DTR

This bit controls the Data Terminal Ready (nDTR) output. When bit 0

is set to a logic “1”, the nDTR output is forced to a logic “0”. When bit

0 is a logic “0”, the nDTR output is forced to a logic “1”.

R/W

RESET

Offset

05h

Bits

Description

Type

Default

Reset

Event

7 FIFO_ERROR

This bit is permanently set to logic “0” in the 450 mode. In the

FIFO mode, this bit is set to a logic “1” when there is at least one

parity error, framing error or break indication in the FIFO. This bit

is cleared when the LSR is read if there are no subsequent errors

in the FIFO.

R0h

RESET

6 TRANSMIT_ERROR

Transmitter Empty. Bit 6 is set to a logic “1” whenever the Trans-

mitter Holding Register (THR) and Transmitter Shift Register

(TSR) are both empty. It is reset to logic “0” whenever either the

THR or TSR contains a data character. Bit 6 is a read only bit. In

the FIFO mode this bit is set whenever the THR and TSR are both

empty,

R0h

RESET

5 TRANSMIT_EMPTY

Transmitter Holding Register Empty Bit 5 indicates that the Serial

Port is ready to accept a new character for transmission. In addi-

tion, this bit causes the Serial Port to issue an interrupt when the

Transmitter Holding Register interrupt enable is set high. The

THRE bit is set to a logic “1” when a character is transferred from

the Transmitter Holding Register into the Transmitter Shift Regis-

ter. The bit is reset to logic “0” whenever the CPU loads the Trans-

mitter Holding Register. In the FIFO mode this bit is set when the

XMIT FIFO is empty, it is cleared when at least 1 byte is written to

the XMIT FIFO. Bit 5 is a read only bit.

R0h

RESET

4 BREAK_INTERRUPT

Break Interrupt. Bit 4 is set to a logic “1” whenever the received

data input is held in the Spacing state (logic “0”) for longer than a

full word transmission time (that is, the total time of the start bit +

data bits + parity bits + stop bits). The BI is reset after the CPU

reads the contents of the Line Status Register. In the FIFO mode

this error is associated with the particular character in the FIFO it

applies to. This error is indicated when the associated character is

at the top of the FIFO. When break occurs only one zero character

is loaded into the FIFO. Restarting after a break is received,

requires the serial data (RXD) to be logic “1” for at least 1/2 bit

time.

Bits 1 through 4 are the error conditions that produce a Receiver

Line Status Interrupt BIT 3 whenever any of the corresponding

conditions are detected and the interrupt is enabled

R0h

RESET

Offset

04h

Bits

Description

Type

Default

Reset

Event

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