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MEC1322 датащи(PDF) 192 Page - Microchip Technology |
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MEC1322 датащи(HTML) 192 Page - Microchip Technology |
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192 / 456 page ![]() MEC1322 DS00001719D-page 192 2014 - 2015 Microchip Technology Inc. 15.0 EC INTERRUPT AGGREGATOR 15.1 Introduction The EC Interrupt Aggregator works in conjunction with the processor’s interrupt interface to handle hardware interrupts and exceptions. Exceptions are synchronous to instructions, are not maskable, and have higher priority than interrupts. All three excep- tions - reset, memory error, and instruction error - are hardwired directly to the processor. Interrupts are typically asyn- chronous and are maskable. Interrupts classified as wake events can be recognized without a running clock, e.g., while the MEC1322 is in sleep state. This chapter focuses on the EC Interrupt Aggregator. Please refer to embedded controller’s documentation for more information on interrupt and exception handling. 15.2 References None 15.3 Terminology None 15.4 Interface FIGURE 15-1: BLOCK DIAGRAM OF EC Interrupt Aggregator GIRQ8 Source Register GIRQ9 Source Register GIRQ10 Source Register GIRQ23 Source Register 31 31 31 Interrupt Sources AOI AOI AOI AOI Masking Bits Masking Bits Masking Bits Masking Bits Processor 16 31 |
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