MEC1322 datasheet(184/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 184

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14.11.5

INTERRUPT ENABLE REGISTER

The lower four bits of this register control the enables of the five interrupt sources of the Serial Port interrupt. It is possible

to totally disable the interrupt system by resetting bits 0 through 3 of this register. Similarly, setting the appropriate bits

of this register to a high, selected interrupts can be enabled. Disabling the interrupt system inhibits the Interrupt Identi-

fication Register and disables any Serial Port interrupt out of the MEC1322. All other system functions operate in their

normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register

are described below.

14.11.6

FIFO CONTROL REGISTER

This is a write only register at the same location as the Interrupt Identification Register.

Offset

01h (DLAB=0)

Bits

Description

Type

Default

Reset

Event

7:4 Reserved

3EMSI

This bit enables the MODEM Status Interrupt when set to logic “1”.

This is caused when one of the Modem Status Register bits changes

state.

R/W

RESET

2ELSI

This bit enables the Received Line Status Interrupt when set to logic

“1”. The error sources causing the interrupt are Overrun, Parity,

Framing and Break. The Line Status Register must be read to deter-

mine the source.

R/W

RESET

1ETHREI

This bit enables the Transmitter Holding Register Empty Interrupt

when set to logic “1”.

R/W

RESET

0 ERDAI

This bit enables the Received Data Available Interrupt (and timeout

interrupts in the FIFO mode) when set to logic “1”.

R/W

RESET

Note:

DMA is not supported.

Offset

02h

Bits

Description

Type

Default

Reset

Event

7:6 RECV_FIFO_TRIGGER_LEVEL

These bits are used to set the trigger level for the RCVR FIFO inter-

rupt.

W0h

RESET

5:4 Reserved

3 DMA_MODE_SELECT

Writing to this bit has no effect on the operation of the UART. The

RXRDY and TXRDY pins are not available on this chip.

W0h

RESET

2 CLEAR_XMIT_FIFO

Setting this bit to a logic “1” clears all bytes in the XMIT FIFO and

resets its counter logic to “0”. The shift register is not cleared. This

bit is self-clearing.

W0h

RESET

1 CLEAR_RECv_FIFO

Setting this bit to a logic “1” clears all bytes in the RCVR FIFO and

resets its counter logic to “0”. The shift register is not cleared. This

bit is self-clearing.

W0h

RESET

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