MEC1322 datasheet(182/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 182

 2014 - 2015 Microchip Technology Inc.

14.10.2

CONFIGURATION SELECT REGISTER

14.11 Runtime Registers

The registers listed in the Runtime Register Summary table are for a single instance of the UART. The addresses of

each register listed in this table are defined as a relative offset to the host “Base Address” defined in Runtime Register

Base Address Table.

Note 14-1

The Base Address indicates where the first register can be accessed in a particular address space

for a block instance.

Note 14-2

DLAB is bit 7 of the Line Control Register.

Offset

F0h

Bits

Description

Type

Default

Reset

Event

7:3 Reserved

2POLARITY

1=The UART_TX and UART_RX pins functions are inverted

0=The UART_TX and UART_RX pins functions are not inverted

R/W

RESET

1POWER

1=The RESET reset signal is derived from nSIO_RESET

0=The RESET reset signal is derived from VCC1_RESET

R/W

RESET

0 CLK_SRC

1=The UART Baud Clock is derived from an external clock source

0=The UART Baud Clock is derived from one of the two internal clock

sources

R/W

RESET

TABLE 14-10: RUNTIME REGISTER BASE ADDRESS TABLE

Block Instance

Instance

Number

Host

Address Space

Base Address (

Note 14-1)

UART

LPC

I/O

Programmed BAR

32-bit internal

address space

400F_1C00h

TABLE 14-11: RUNTIME REGISTER SUMMARY

DLAB

(

Note 14-2)

Offset

00h

Receive Buffer Register

00h

Transmit Buffer Register

10h

Programmable Baud Rate Generator LSB Register

11h

Programmable Baud Rate Generator MSB Register

01h

Interrupt Enable Register

x02h

FIFO Control Register

x02h

Interrupt Identification Register

x03h

Line Control Register

x04h

Modem Control Register

x05h

Line Status Register

x06h

Modem Status Register

x07h

Scratchpad Register

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