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MEC1322 датащи(PDF) 273 Page - Microchip Technology |
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MEC1322 датащи(HTML) 273 Page - Microchip Technology |
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273 / 456 page ![]() 2014 - 2015 Microchip Technology Inc. DS00001719D-page 273 MEC1322 22.6 Host Interface The registers defined for the SMBus Interface are accessible as indicated in Section 22.12, "SMBus Registers". 22.7 DMA Interface This block is designed to communicate with the Internal DMA Controller. This feature is defined in the SMBus Controller Core Interface specification (See Ref [1]). Note: For a description of the Internal DMA Controller implemented in this design see Chapter 21.0, "Internal DMA Controller". 22.8 Power, Clocks and Reset This section defines the Power, Clock, and Reset parameters of the block. 22.8.1 POWER DOMAINS 22.8.2 CLOCK INPUTS 22.8.3 RESETS 22.9 Interrupts 22.10 Low Power Modes The SMBus Interface may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry. 22.11 Description 22.11.1 SMBUS CONTROLLER CORE The MEC1322 SMBus Interface behavior is defined in the SMBus Controller Core Interface specification (See Ref [1]). TABLE 22-2: SIGNAL TO PIN NAME LOOKUP TABLE Block Name Pin Name Description SMBx_DATn I2Cx_DATn SMBus Controller x Port n Data SMBx_CLKn I2Cx_CLKn SMBus Controller x Port n Clock TABLE 22-3: POWER SOURCES Name Description VCC1 This power well sources the registers and logic in this block. TABLE 22-4: CLOCK INPUTS Name Description 48 MHz Ring Oscillator This is the clock signal drives the SMBus controller core. The core also uses this clock to generate the SMB_CLK on the pin interface. 16MHz_Clk This is the clock signal is used for baud rate generation. TABLE 22-5: RESET SIGNALS Name Description VCC1_RESET This reset signal resets all of the registers and logic in the SMBus controller core. TABLE 22-6: EC INTERRUPTS Source Description SMB SMBus Activity Interrupt Event |
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