MEC1322 datasheet(219/456 Pages) MICROCHIP

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DS00001719D-page 219

MEC1322

16.6

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

16.6.1

POWER DOMAINS

16.6.2

CLOCK INPUTS

16.6.3

RESETS

16.7

Description

16.7.1

WDT OPERATION

16.7.1.1

WDT Activation Mechanism

The WDT is activated by the following sequence of operations during normal operation:

Load the WDT Load Register with the count value.

Set the WDT Enable bit in the WDT Control Register.

The WDT Activation Mechanism starts the WDT decrementing counter.

16.7.1.2

WDT Deactivation Mechanism

The WDT is deactivated by the clearing the WDT Enable bit in the WDT Control Register. The WDT Deactivation Mech-

anism places the WDT in a low power state in which clock are gated and the counter stops decrementing.

16.7.1.3

WDT Reload Mechanism

The WDT must be reloaded within periods that are shorter than the programmed watchdog interval; otherwise, the WDT

will underflow and a WDT Event will be generated and the WDT Status bit will be set in the WDT Control Register. It is

the responsibility of the user program to continually execute code which reloads the watchdog timer, causing the counter

to be reloaded

There are three methods of reloading the WDT: a write to the WDT Load Register, a write to the WDT Kick Register, or

WDT event.

TABLE 16-1:

POWER SOURCES

Name

Description

VCC1

The logic and registers implemented in this block reside on this single

power well.

TABLE 16-2:

CLOCK INPUTS

Name

Description

32KHz_Clk

The 32KHz_Clk clock input is the clock source to the Watchdog Timer

functional logic, including the counter.

TABLE 16-3:

RESET SIGNALS

Name

Description

VCC1_RESET

Power on Reset to the block. This signal resets all the register and logic

in this block to its default state.

TABLE 16-4:

RESET OUTPUT EVENT

Source

Description

WDT Event

Pulse generated when WDT expires. This signal is used to reset the

embedded controller and its subsystem.

The event is cleared after an VCC1_RESET.

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