UPD750064CU datasheet(67/82 Pages) NEC

67 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85˚C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Release signal set time

tSREL

µs

Oscillation stabilization

tWAIT

Released by RESET

Note 2

wait timeNote 1

Released by interrupt request

Note 3

Notes 1.

The oscillation stabilization wait time is the time during which the CPU stops operating to prevent

unstable operation when oscillation is started.

Either 217/fX or 215/fX can be selected by mask option.

Set by the basic interval timer mode register (BTM). (Refer to the table below.)

BTM3

BTM2

BTM1

BTM0

Wait Time

fX = 4.19 MHz

fX = 6.0 MHz

–000

220/fX (approx. 250 ms)

220/fX (approx. 175 ms)

–011

217/fX (approx. 31.3 ms)

217/fX (approx. 21.8 ms)

–101

215/fX (approx. 7.81 ms)

215/fX (approx. 5.46 ms)

–111

213/fX (approx. 1.95 ms)

213/fX (approx. 1.37 ms)

Data retention timing (STOP mode release by RESET)

Data retention timing (standby release signal: STOP mode release by interrupt signal)

STOP mode

Data retention mode

Internal reset operation

Operation mode

STOP instruction execution

HALT mode

VDD

RESET

VDDDR

tWAIT

tSREL

STOP mode

Data retention mode

Operation mode

HALT mode

tSREL

VDDDR

tWAIT

STOP instruction execution

VDD

Standby release signal

(interrupt request)

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