UPD750064CU datasheet(37/82 Pages) NEC

37 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

8. STANDBY FUNCTION

In order to save power dissipation while a program is in a standby mode, two types of standby modes (STOP

mode and HALT mode) are provided for the

µPD750068.

Table 8-1. Operation Status in Standby Mode

Mode

STOP Mode

HALT Mode

Item

Set instruction

STOP instruction

HALT instruction

System clock when set

Settable only when the main system

Settable both by the main system clock

clock is used.

and subsystem clock.

Operation

Clock generator

The main system clock stops oscillation.

Only the CPU clock

Φ halts (oscillation

status

continues).

Basic interval timer/

Operation stops.

Operable only when the main system

watchdog timer

clock is oscillated (The IRQBT is set in

the reference time interval).

Serial interface

Operable only when an external SCK

input is selected as the serial clock.

input is selected as the serial clock or

when the main system clock is oscillated.

Timer/event counter

Operable only when a signal input to

the TI0 and TI1 pins or a watch timer

which selected fXT is specified as the

count clock.

count clock or when the main system

clock is oscillated.

Watch timer

Operable when fXT is selected as the

Operable.

count clock.

A/D converter

Operation stops.

Operable only when the main system

clock is oscillated.

External interrupt

The INT1, 2, and 4 are operable.

Only the INT0 is not operatedNote.

CPU

Operation stops.

Release signal

• Interrupt request signal sent from the operable hardware enabled by the interrupt

enable flag.

• Test request signal sent from the test source enabled by the test enable flag

• RESET signal generation

Note

Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection

mode register (IM0).

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