UPD750064CU datasheet(44/82 Pages) NEC

44 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

(3) Explanation of symbols under addressing area column

MB = MBE•MBS (MBS = 0, 1, 15)

MB = 0

MBE = 0 : MB = 0 (000H to 07FH)

MB = 15 (F80H to FFFH)

Data memory addressing

MBE = 1 : MB = MBS (MBS = 0, 1, 15)

MB = 15, fmem = FB0H to FBFH, FF0H to FFFH

MB = 15, pmem = FC0H to FFFH

addr = 0000H to 0FFFH (

µPD750064)

0000H to 17FFH (

µPD750066)

0000H to 1FFFH (

µPD750068)

addr, addr1 = (Current PC) – 15 to (Current PC) – 1

(Current PC) + 2 to (Current PC) + 16

caddr = 0000H to 0FFFH (

µPD750064)

0000H to 0FFFH (PC12 = 0:

µPD750066, 750068)

1000H to 17FFH (PC12 = 1:

µPD750066)

Program memory addressing

1000H to 1FFFH (PC12 = 1:

µPD750068)

faddr = 0000H to 07FFH

*10

taddr = 0020H to 007FH

*11

Mk II mode only

addr1 = 0000H to 0FFFH (

µPD750064)

0000H to 17FFH (

µPD750066)

0000H to 1FFFH (

µPD750068)

Remarks 1.

MB indicates memory bank that can be accessed.

In *2, MB = 0 independently of how MBE and MBS are set.

In *4 and *5, MB = 15 independently of how MBE and MBS are set.

*6 to *11 indicate the areas that can be addressed.

(4) Explanation of number of machine cycles column

S denotes the number of machine cycles required by skip operation when a skip instruction is executed.

The value of S varies as follows.

•

When no skip is made: S = 0

•

When the skipped instruction is a 1- or 2-byte instruction: S = 1

•

When the skipped instruction is a 3-byte instructionNote: S = 2

Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction

Caution The GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle (= tCY) of CPU clock

Φ; time can be selected from among four

types by setting PCC.

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