| поискавой системы для электроныых деталей |
|
UPD750064CU датащи(PDF) 40 Page - NEC |
|
|
|||||||||||||||||||||||||||||
UPD750064CU датащи(HTML) 40 Page - NEC |
|
40 / 82 page ![]() 40 µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Data Sheet U10165EJ2V0DS00 Table 9-1. Status of Each Hardware After Reset (2/2) Hardware RESET Signal Generation RESET Signal Generation in Standby Mode in Operation Serial interface Shift register (SIO) Held Undefined Operation mode register (CSIM) 00 SBI control register (SBIC) 0 0 Clock generator, Processor clock control register (PCC) 0 0 clock output System clock control register (SCC) 0 0 circuit Clock output mode register (CLOM) 0 0 Sub-oscillator control register (SOS) 0 0 A/D converter Mode register (ADM) 04H 04H SA register (SA) 7FH 7FH Interrupt Interrupt request flag (IRQ ×××) Reset (0) Reset (0) function Interrupt enable flag (IE ×××)0 0 Interrupt priority selection register (IPS) 00 INT0, 1, 2 mode registers (IM0, IM1, IM2) 0, 0, 0 0, 0, 0 Digital port Output buffer Off Off Output latch Cleared (0) Cleared (0) I/O mode registers (PMGA, PMGB) 0 0 Pull-up resistor setting register (POGA) 00 Bit sequential buffer (BSB0 to BSB3) Held Undefined |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |