UPD750064CU datasheet(6/82 Pages) NEC

6 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

1. PIN CONFIGURATION (Top View)

•

42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

µPD750064CU-×××, µPD750064CU(A)-×××

µPD750066CU-×××, µPD750066CU(A)-×××

µPD750068CU-×××, µPD750068CU(A)-×××

•

42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)

µPD750064GT-×××, µPD750064GT(A)-×××

µPD750066GT-×××, µPD750066GT(A)-×××

µPD750068GT-×××, µPD750068GT(A)-×××

XT1

XT2

RESET

P33

P32

P31

P30

AVSS

P63/KR3/AN7

P62/KR2/AN6

P61/KR1/AN5

P60/KR0/AN4

P113/AN3

P112/AN2

P111/AN1

P110/AN0

AVREF

VDD

VSS

P40

P41

P42

P43

P50

P51

P52

P53

P00/INT4

P01/SCK

P02/SO/SB0

P03/SI/SB1

P10/INT0

P11/INT1

P12/TI1/INT2

P13/TI0

P20/PTO0

P21/PTO1

P22/PCL

P23/BUZ

IC: Internally Connected (Connect pin directly to VDD).

Pin Identification

AN0 to AN7

: Analog Input 0 to 7

AVREF

: Analog Reference

AVSS

: Analog Ground

BUZ

: Buzzer Clock

: Internally Connected

INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4

INT2

: External Test Input 2

KR0 to KR3

: Key Return 0 to 3

P00 to P03

: Port 0

P10 to P13

: Port 1

P20 to P23

: Port 2

P30 to P33

: Port 3

P40 to P43

: Port 4

P50 to P53

: Port 5

P60 to P63

: Port 6

P110 to P113

: Port 11

PCL

: Programmable Clock

PTO0, PTO1

: Programmable Timer Output 0, 1

RESET

: Reset Input

SB0, SB1

: Serial Data Bus 0, 1

SCK

: Serial Clock

: Serial Input

: Serial Output

TI0, TI1

: Timer Input 0, 1

VDD

: Positive Power Supply

VSS

: Ground

X1, X2

: Main System Clock Oscillation 1, 2

XT1, XT2

: Subsystem Clock Oscillation 1, 2

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