UPD750064CU datasheet(60/82 Pages) NEC

60 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

DC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply currentNote 1

IDD1

VDD = 5.0 V

±10%Note 3

2.2

6.6

VDD = 3.0 V

±10%Note 4

0.48

1.5

IDD2

HALT

VDD = 5.0 V

±10%

0.86

2.6

mode

VDD = 3.0 V

±10%

0.43

1.3

IDD1

VDD = 5.0 V

±10%Note 3

1.7

4.5

VDD = 3.0 V

±10%Note 4

0.4

1.2

IDD2

HALT

VDD = 5.0 V

±10%

0.7

mode

VDD = 3.0 V

±10%

0.39

1.2

IDD3

Low-

VDD = 3.0 V

±10%

µA

voltage

VDD = 2.0 V

±10%

5.5

µA

modeNote 6

VDD = 3.0 V, TA = 25˚C

µA

VDD = 3.0 V

±10%

9.2

µA

VDD = 3.0 V, TA = 25˚C

9.2

µA

IDD4

HALT

Low-

VDD = 3.0 V

±10%

6.4

µA

mode

voltage

VDD = 2.0 V

±10%

2.5

µA

modeNote 6 VDD = 3.0 V, TA = 25˚C

6.4

12.8

µA

VDD = 3.0 V

±10%

4.6

13.8

µA

VDD = 3.0 V, TA = 25˚C

4.6

9.2

µA

IDD5

XT1 =

VDD = 5.0 V

±10%

0.05

µA

0 VNote 8

VDD = 3.0 V

±10%

0.02

µA

STOP mode

TA = 25˚C

0.02

µA

Notes 1.

The current flowing to the internal pull-up resistor is not included.

Including the case when the subsystem clock oscillates.

When the device operates in high-speed mode with the processor clock control register (PCC) set to

0011.

When the device operates in low-speed mode with PCC set to 0000.

When the device operates on the subsystem clock, with the system clock control register (SCC) set

to 1001 and oscillation of the main system clock stopped.

When the sub-oscillation circuit control register (SOS) is set to 0000.

When SOS is set to 0010.

When SOS is set to 00

×1, and the sub-oscillation circuit feedback resistor is not used (×: don’t care).

6.0-MHzNote 2

crystal

oscillation

C1 = C2

= 22 pF

4.19-MHz

Note 2

crystal

oscillation

C1 = C2

= 22 pF

32.768-

kHzNote 5

crystal

oscillation

Low current

dissipation

modeNote 7

Low current

dissipation

modeNote 7

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