UPD750064CU datasheet(56/82 Pages) NEC

56 / 82 page

µPD750064, 750066, 750068, 750064(A), 750066(A), 750068(A)

Data Sheet U10165EJ2V0DS00

Main System Clock Oscillator Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Resonator

Recommended

Parameter

Conditions

MIN.

TYP.

MAX.

Unit

Constants

Ceramic

Oscillation frequency

1.0

6.0Note 2

MHz

resonator

(fX)Note 1

Oscillation

After VDD reaches

stabilization timeNote 3

oscillation voltage

range MIN. value

Crystal

Oscillation frequency

1.0

6.0Note 2

MHz

resonator

(fX)Note 1

Oscillation

VDD = 4.5 to 5.5 V

stabilization timeNote 3

External

X1 input frequency

1.0

6.0Note 2

MHz

clock

(fX)Note 1

X1 input high-/

83.3

500

low-level width

(tXH, tXL)

Notes 1.

The oscillation frequency and X1 input frequency shown above indicate only oscillator characteristics.

Refer to AC Characteristics for instruction execution time.

If the oscillation frequency is 4.19 MHz < fX

≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V, do not select the processor

clock control register (PCC) = 0011. If PCC = 0011, one machine cycle time is less than 0.95

µs, falling

short of the rated value of 0.95

µs.

The oscillation stabilization time is the time required to stabilize oscillation after VDD has been applied

or STOP mode has been released.

Caution When using the main system clock oscillator, wire as follows in the area enclosed by the broken

lines in the above figures to avoid an adverse effect from wiring capacitance.

•

Keep the wiring length as short as possible.

•

Do not cross the wiring with the other signal lines.

•

Do not route the wiring near a signal line through which a high fluctuating current flows.

•

Always make the ground point of the oscillator capacitor the same potential as VSS.

•

Do not ground the capacitor to a ground pattern through which a high current flows.

•

Do not fetch signals from the oscillator.

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