GDC21D301A datasheet(7/35 Pages) HYNIX

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GDC21D301A

Pin Description (continued)

NAME

TYPE

DESCRIPTION

HIGH SPEED DATA INTERFACE

\ERR_BLOCK

FEC Packet Error (active low).

This optional signal may be used to declare that the

error has

occurred

packet.

used

place

transport_error_indicator bit in the TS header by the equipment

interfacing with the GDC21D301A.

D_VALID

FEC Data Valid.

This signal indicates that the data value of FEC_DATA bus is

valid transport stream byte or serial bit. It will be latched in the

internal buffer on the rising edge of FEC_CLOCK.

HSDEN

High Speed Port Data Enable

HIGH_SP_DATA

[1:0]

12, 13

High Speed Port Data

CLOCK RECOVERY INTERFACE

VPWM

126

Pulse Width Modulated Pulse1.

Low pass filtered VPWM signal is fed to external VCXO for

adjusting its output frequency.

APWM

101

Pulse Width Modulated Pulse2.

This is used to lock the Audio clock in the Video clock for lip

synchronization. Low pass filtered APWM signal is fed to the

VCXO.

DRAM INTERFACE

M16

DRAM 16-Mbit Configuration

DRAM_RWB

DRAM Read/Write.

When you access DRAM, read mode or write mode

can be

set as following.

0 : Write mode

1 : Read mode

DRAM_ROW_COL_

ADDR[9:0]

50,51,52,54,

55,56,57,59,

60,61

DRAM Parallel Address Bus [9:0].

Row-column address is multiplexed when you access external

DRAM. For the fast page mode access, row address is applied

first, and column address is applied next.

DRAM_DATA[15:0]

67,73,74,75,

76,78,79,80,

81,83,84,85,

86,88,89,90

I/O/Z

DRAM Parallel Data Bus [15:0].

\DRAM_RAS0

DRAM Row Address Strobe0.

Select DRAM0 device. When this signal goes to low, DRAM_

ROW_COL_-ADDR[9:0] has a valid row address.

\DRAM_RAS1

DRAM Row Address Strobe1.

Select the DRAM1 device. When this signal goes to low,

DRAM_ROW_COL_-ADDR[9:0] has a valid row address.

\DRAM_CAS0

DRAM Column Address Strobe0.

Select the low byte DRAM data. When this signal goes to low,

DRAM_-ROW_COL_ADDR[9:0] has a valid column address.

\DRAM_CAS1

DRAM Column Address Strobe1.

Select the high byte DRAM data. When this signal goes to low,

DRAM_-ROW_COL_ADDR[9:0] has a valid column address.

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