GDC21D301A datasheet(24/35 Pages) HYNIX

24 / 35 page

GDC21D301A

PID Registers (0x400 ~ 0x47e)

These registers should be written with certain

values during initialization phase, because the

values are undefined at first. Video, audio, and

auxiliary packet will be respectively transferred to

VAD_DATA port with VID_STRB, AUD_STRB,

and DATA_STRB signal in case Hig bit in the

priority. This is equally applied to other packets.).

Other data will be transferred to the corresponding

buffer in DRAM.

Vid PID Register (0x400, 0x402)

These registers should be written with certain

values during initialization phase, because the

values are undefined at first. For correct processing,

Dst should be written to ‘0’.

Field

Bits

Description

Values

Default

Den

PID enable

1 = PID matching enabled

Dst

Decoding state(status reg.)

1 = corresponding PID packet

occurred at least once before

Frm

Decoding Type

0 = transfer PES_payload to

external port

1 = transfer whole PES packet

PID

12:0

PID

These registers should be written with certain

values during initialization phase, because the

values are undefined at first.

Field

Bits

Description

Values

Default

Hig

High Speed out enable

1 = transfer whole TS packet to

high speed port

CCNT

3:0

Continuity Counter

store continuity_counter value

Aud PID Register (0x404, 0x406)

Same as Vid PID register, but Audio packet

Aux PID Register (0x408, 0x40a)

Same as Vid PID register, but Auxiliary packet

Den Dst Frm

PID

Hig

CCNT

GDC21D301A датащи(PDF) 24 Page - Hynix Semiconductor

GDC21D301A датащи(HTML) 24 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

датащи скачать

ссылки URL