GDC21D301A datasheet(13/35 Pages) HYNIX

13 / 35 page

GDC21D301A

5.6 Memory Controller

This controls DRAM interface. It refreshes

DRAM, writes and reads data to and from

DRAM. The corresponding addresses where

the data is written and read are stored in

pointer memory by the Host processor. The

GDC21D301A requires one or two DRAMs

(256Kx16b or 1Mx16b).

\DRAM_RAS0

\DRAM_CAS0

\RAS

\LCAS

DRAM_DATA [15:0]

DATA [15:0]

DRAM_ADDR [9:0]

ADDR [9:0]

DRAM_RWB

RWB

DRAM 0

(256Kx16 or 1Mx16)

DRAM 1

M 16

GDC21D301

\DRAM_RAS1

\DRAM_CAS1

\UCAS

\RAS

\LCAS

DATA [15:0]

ADDR [9:0]

RWB

\UCAS

Figure 3. External DRAM Interface

5.7 High-Speed Interface

This is an interface block of external high-speed

ports which send whole TS packets.

5.8 External Decoder Interface

This reads data from buffer and sends it to the

corresponding external decoder. It also controls the

input/output of data to and from external decoder.

5.9 Host Interface

Host Processor can access external decoders

through the GDC21D301A transport decoder.

DSP_DATA[15:0] ports are used for data bus.

To access one of the external decoders through the

GDC21D301A,

host

address

bus

(DSP_ADDR[22:0]) should be as follows.

For video decoder access,

DSP_ADDR[22:18] = “100 11”.

For audio decoder access,

DSP_ADDR[22:18] = “100 01”.

For auxiliary decoder access,

DSP_ADDR[21:18] = “100 00”.

5.10 Clock Controller

It outputs two PWM signals(VPWM and APWM)

which can be controlled by the Host Processor. The

PWM signals can be used to control external

VCXOs.

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