GDC21D301A datasheet(14/35 Pages) HYNIX

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GDC21D301A

6. Register Description

This

chapter

describes

the

registers

the

GDC21D301A. Table 1 summarizes these registers.

Note the following general information:

• All registers are 16-bit wide and can read/write

unless especially noted.

• All accesses to internal registers are allowed by

word or byte using DSP_ADDR[0] pin which

determines access mode unit.

• The reserved bits should be written to zero to

preserve compatibility with future features.

• Register addresses that are not defined in Table 1

are reserved. Read from these locations causes

unpredictable results. It is recommended not to

access these registers.

• In order to access these register, you should

set DSP_ADDR[22:18] to “100 11”.

Table 1. Register Summary

ADDR[A10:A0] R/W

REGISTERS

DEFINITION

000

R/W

Interrupt Flag 1

Indicates active interrupts

002

R/W

Interrupt Flag 2

Indicates active interrupts

004

R/W

Interrupt Mask 1

Interrupt Enable

006

R/W

Interrupt Mask 2

Interrupt Enable

008

R/W

Instruction

Controls the decoding

00a

R/W

Round Buffer

Controls Buffer Management

00c

PID Flag 1

Current Packet transferred

00e

PID Flag 2

Current Packet transferred

010

R/W

PWM control 1

Controls PWM output

012

R/W

PWM control 2

Controls PWM output

014

R/W

Sync Hysterisis

Sets lock/unlock parameters for sync detect

02a ~ 02e

PTS

PTS of Current Packet transferred

030 ~ 034

DTS

DTS of Current Packet transferred

036 ~ 03c

PCR

PCR of Current Packet transferred

040

splicing_count_ down

Current Splicing Countdown transferred

042,044

ES_rate

Current ES rate transferred

046

DSM_trick_mode

Current DSM trick mode transferred

048

additional_copy_info

Additional copy information

060,062

STC 1