GDC21D301A datasheet(6/35 Pages) HYNIX

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GDC21D301A

(Package : 176TQFP)

NAME

TYPE

DESCRIPTION

CLOCKS & RESET

CLOCK

157

Operation clock.

The frequency of operating clock is 27MHz and it should be

locked in encoder system clock. The clock may be supplied by

external VCXO controlled by VPWM.

CLOCK_27M

27MHz clock.

It is used to count STC value. This clock may be supplied by

external VCXO controlled by VPWM.

CLOCK_OUT

Operation Clock Output.

For high-speed output data

\RESET

112

Global Reset (active low)

The signal asynchronously resets the GDC21D301A.

TEST INTERFACE (for IC self-test purpose only)

TEST

Test Mode

TA[9:0]

46,44,16,17,

18,19,20,21,2

2,23

Test address.

TA[9] and TA[8] are respectively multiplexed with SCAN_IN1

and SCAN_MODE pins.

TDI

Test Input Data

TWEB

Test Write Enable (active low)

TDO0

Test Output Data0

TDO1

Test Output Data1

TRANSPORT STREAM INTERFACE

P_S_MODE

FEC Data Input Mode Selection.

0: byte-parallel input mode

1: bit-serial input mode

FEC_DATA[7:0]

30,31,36,37,

38,39,40,41

TS Data.

It is used for byte-parallel or bit-serial transfers of a coded TS

data to the device. In bit-serial mode, FEC_DATA[0] is a serial

data input for TS data.

F_START

FEC Sync Byte Indicator.

F_START is valid in bit-serial input mode only.

FEC_DATA

is aligned by the byte parallel with this signal. This signal

should be activated at the first bit of the TS sync byte or every

first bit of the data byte.

FEC_CLOCK

FEC Data Clock.

FEC_CLOCK is used to latch a data byte or a single bit of

coded TS into the device on the rising edge. FEC_CLOCK may

be asynchronous with the device. The value of FEC_DATA is

locked into the GDC21D301A internal buffer on the rising

edge of FEC_CLOCK, if D_VALID is asserted HIGH.

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