MPC7457 datasheet(6/71 Pages) FREESCALE

6 / 71 page

MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8

Features

Freescale Semiconductor

— Space must be available in the CQ for an instruction to dispatch (this includes instructions that

are assigned a space in the CQ but not in an issue queue)

•

Rename buffers

— 16 GPR rename buffers

— 16 FPR rename buffers

— 16 VR rename buffers

•

Dispatch unit

— Decode/dispatch stage fully decodes each instruction

•

Completion unit

— The completion unit retires an instruction from the 16-entry completion queue (CQ) when all

instructions ahead of it have been completed, the instruction has finished execution, and no

exceptions are pending.

— Guarantees sequential programming model (precise exception model)

— Monitors all dispatched instructions and retires them in order

— Tracks unresolved branches and flushes instructions after a mispredicted branch

— Retires as many as three instructions per clock cycle

•

Separate on-chip L1 instruction and data caches (Harvard architecture)

— 32-Kbyte, eight-way set associative instruction and data caches

— Pseudo least recently used (PLRU) replacement algorithm

— 32-byte (eight-word) L1 cache block

— Physically indexed/physical tags

— Cache write-back or write-through operation programmable on a per-page or per-block basis

— Instruction cache can provide four instructions per clock cycle; data cache can provide four

words per clock cycle

— Caches can be disabled in software.

— Caches can be locked in software.

— MESI data cache coherency maintained in hardware

— Separate copy of data cache tags for efficient snooping

— L1 cache supports parity generation and checking

— No snooping of instruction cache except for icbi instruction

— Data cache supports AltiVec LRU and transient instructions

— Critical double- and/or quad-word forwarding is performed as needed. Critical quad-word

forwarding is used for AltiVec loads and instruction fetches. Other accesses use critical

double-word forwarding.

•

Level 2 (L2) cache interface

— On-chip, 512-Kbyte, eight-way set associative unified instruction and data cache

— Fully pipelined to provide 32 bytes per clock cycle to the L1 caches

— A total nine-cycle load latency for an L1 data cache miss that hits in L2

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