MPC7457 datasheet(26/71 Pages) FREESCALE

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MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8

Electrical and Thermal Characteristics

Freescale Semiconductor

5.2.4.2

L3 Bus AC Specifications for DDR MSUG2 SRAMs

When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as shown in Figure 9.

Outputs from the MPC7457 are actually launched on the edges of an internal clock phase-aligned to

SYSCLK (adjusted for core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock

output with 90° phase delay, so outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid

times are typically negative when referenced to L3_CLKn because the data is launched one-quarter period

before L3_CLKn to provide adequate setup time at the SRAM after the delay-matched address, control,

data, and L3_CLKn signals have propagated across the printed-wiring board.

Inputs to the MPC7457 are source-synchronous with the CQ clock generated by the DDR MSUG2

SRAMs. These CQ clocks are received on the L3_ECHO_CLKn inputs of the MPC7457. An internal

circuit delays the incoming L3_ECHO_CLKn signal such that it is positioned within the valid data

L3CLK

n_OH

All signals latched by

SRAM connected to

L3_CLK

0b000

tL3CHOV,

tL3CHDV,

tL3CLDV

0tL3CHOX,

tL3CHDX,

tL3CLDX

0ps

0b001

– 50

0b010

– 100

0b011

– 150

0b100

– 200

0b101

– 250

0b110

– 300

0b111

– 350

L3DOH

L3_DATA[

n:n+7],

L3_DP[

n/8]

0b000

tL3CHDV,

tL3CLDV

0tL3CHDX,

tL3CLDX

0ps

0b001

+ 50

0b010

+ 100

0b011

+ 150

0b100

+ 200

0b101

+ 250

0b111

+ 300

0b111

+ 350

Notes:

1. See the

MPC7450 RISC Microprocessor Family User’s Manual for specific information regarding L3OHCR.

2. See Table 13 and Table 14 for more information.

3. Approximate delay verified by simulation; not tested or characterized.

4. Default value.

5. Increasing values of L3CLK

n_OH delay the L3_CLKn signal, effectively decreasing the output valid and output hold times of

all signals latched relative to that clock signal by the SRAM; see Figure 9 and Figure 11.

Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing (continued)

At recommended operating conditions. See Table 4.

Field Name1

Affected Signals

Value

Output Valid Time

Output Hold Time

Unit

Notes

Parameter

Symbol 2

Change 3

Parameter

Symbol 2

Change 3

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